AD9937 datasheet(28/44 Pages) AD

28 / 44 page

REV. 0

–28–

AD9937

001

002

003

004

000

11-BIT

VD COUNTER

12-BIT

HD COUNTER

PBLK

N – 1

Figure 21. Example with PBLKSTOP = PBLKSTART = 2048

Controlling CLPOB Clamp Pulse Timing

Up to two individual CLPOB pulses can be programmed per line

using the CLPOBTOGx (x = 1, 2, 3, 4) registers in Table XII.

As shown in Figure 19, these registers reference the 12-bit HD

counter. Additional CLPOBENn (n = 0, 1, 2, 3, 4) registers are

provided that allow for independently enabling and disabling

the CLPOB pulse in each region of the CCD. Figure 23 shows

an example of disabling the CLPOB pulse while operating in

CCD region 1.

CLPOB

PROGRAMMABLE CLOCK POSITIONS

1. CLPOBTOG1 (PROGRAMMABLE AT MODE_REG(5))

2. CLPOBTOG2 (PROGRAMMABLE AT MODE_REG(5))

3. CLPOBTOG3 (PROGRAMMABLE AT MODE_REG(6))

4. CLPOBTOG4 (PROGRAMMABLE AT MODE_REG(6))

12-BIT

HD COUNTER

Figure 22. CLPOB Toggle Positions

Table XII. CLPOB Registers

Length

(Bits)

Type

Range

Description

CLPOBTOG1

Mode_Reg(5)

0–4095 Pixel Location

First Toggle Position for CLPOB

CLPOBTOG2

Mode_Reg(5)

0–4095 Pixel Location

First Toggle Position for CLPOB

CLPOBTOG3

Mode_Reg(6)

0–4095 Pixel Location

First Toggle Position for CLPOB

CLPOBTOG4

Mode_Reg(6)

0–4095 Pixel Location

First Toggle Position for CLPOB

CLPOBEN0

Mode_Reg(15)

Enabled/Disabled

CCD Region 0 CLPOB Enable Disable Control

CLPOBEN1

Mode_Reg(16)

Enabled/Disabled

CCD Region 1 CLPOB Enable Disable Control

CLPOBEN2

Mode_Reg(17)

Enabled/Disabled

CCD Region 2 CLPOB Enable Disable Control

CLPOBEN3

Mode_Reg(18)

Enabled/Disabled

CCD Region 3 CLPOB Enable Disable Control

CLPOBEN4

Mode_Reg(19)

Enabled/Disabled

CCD Region 4 CLPOB Enable Disable Control

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