AD9937 datasheet(33/44 Pages) AD

33 / 44 page

REV. 0

AD9937

–33–

MASKING H1 AND H2 OUTPUTS

The H1 and H2 outputs can be masked during the horizontal

and vertical transfers as shown in Figures 29 and 30.

Horizontal Masking

The H1 clocks are masked with the polarity set by the

H1MASKPOL register as shown in Figure 29. The H2 outputs

will always be the opposite polarity of H1. The H1 and H2 out-

puts are masked from HDLEN + 1 to HBLKTOG1 position

when HDLASTLEN is the same as HDLEN. In the case when

HDLASTLEN is greater than HDLEN, the H1 and H2 outputs

will be masked during the entire last line. It is recommended to

always program HBLKTOG3 and HBLKTOG4 to 4095 when

only one H-blanking in a line is required. It is also recommended

to program HBLKTOG1 < HBLKTOG2 < HBLKTOG3 <

HBLKTOG4.

Vertical Masking

As shown in Figure 30, the H1 and H2 outputs remain masked

if the horizontal HMASK is followed by the vertical HMASK

region or if the vertical HMASK region is followed by the hori-

zontal HMASK region.

Table XVI. Special H Pattern Registers

Length

(Bits)

Type

Range

Description

HBLKTOG1

Mode_Reg(7)

0–4095 Pixel Locations

HBLK Toggle Position 1

HBLKTOG2

Mode_Reg(7)

0–4095 Pixel Locations

HBLK Toggle Position 2

HBLKTOG3

Mode_Reg(8)

0–4095 Pixel Locations

HBLK Toggle Position 3

HBLKTOG4

Mode_Reg(8)

0–4095 Pixel Locations

HBLK Toggle Position 4

H1APOL

HLM_Reg(1)

High/Low

H1A Special H Pattern Start Polarity

H1BPOL

HLM_Reg(1)

High/Low

H1B Special H Pattern Start Polarity

H1CPOL

HLM_Reg(1)

High/Low

H1C Special H Pattern Start Polarity

H1DPOL

HLM_Reg(1)

High/Low

H1D Special H Pattern Start Polarity

H2APOL

HLM_Reg(1)

High/Low

H2A Special H Pattern Start Polarity

H2BPOL

HLM_Reg(1)

High/Low

H2B Special H Pattern Start Polarity

SPHSTART0

8HLM_Reg(8)

0–255 Pixel Locations

LM Pattern #0 (LM0) Special H Pulse Start Position

SPHSTART1

8HLM_Reg(9)

0–255 Pixel Locations

LM Pattern #1 (LM1) Special H Pulse Start Position

SPH1A1

HLM_Reg(2)

6 Individual Bits

H1A Special H Pattern during LM Repetition 1

SPH1B1

HLM_Reg(2)

6 Individual Bits

H1B Special H Pattern during LM Repetition 1

SPH1C1

HLM_Reg(2)

6 Individual Bits

H1C Special H Pattern during LM Repetition 1

SPH1D1

HLM_Reg(3)

6 Individual Bits

H1D Special H Pattern during LM Repetition 1

SPH2A1

HLM_Reg(3)

6 Individual Bits

H2A Special H Pattern during LM Repetition 1

SPH2B1

HLM_Reg(3)

6 Individual Bits

H2B Special H Pattern during LM Repetition 1

SPH1A2

HLM_Reg(4)

6 Individual Bits

H1A Special H Pattern during LM Repetition 2

SPH1B2

HLM_Reg(4)

6 Individual Bits

H1B Special H Pattern during LM Repetition 2

SPH1C2

HLM_Reg(4)

6 Individual Bits

H1C Special H Pattern during LM Repetition 2

SPH1D2

HLM_Reg(5)

6 Individual Bits

H1D Special H Pattern during LM Repetition 2

SPH2A2

HLM_Reg(5)

6 Individual Bits

H2A Special H Pattern during LM Repetition 2

SPH2B2

HLM_Reg(5)

6 Individual Bits

H2B Special H Pattern during LM Repetition 2

SPH1A3

HLM_Reg(6)

6 Individual Bits

H1A Special H Pattern during LM Repetition 3

SPH1B3

HLM_Reg(6)

6 Individual Bits

H1B Special H Pattern during LM Repetition 3

SPH1C3

HLM_Reg(6)

6 Individual Bits

H1C Special H Pattern during LM Repetition 3

SPH1D3

HLM_Reg(7)

6 Individual Bits

H1D Special H Pattern during LM Repetition 3

SPH2A3

HLM_Reg(7)

6 Individual Bits

H2A Special H Pattern during LM Repetition 3

SPH2B3

HLM_Reg(7)

6 Individual Bits

H2B Special H Pattern during LM Repetition 3

SPHEN0

Mode_Reg(15)

High/Low

Special H Pattern Enable in CCD Region 0

SPHEN1

Mode_Reg(16)

High/Low

Special H Pattern Enable in CCD Region 1

SPHEN2

Mode_Reg(17)

High/Low

Special H Pattern Enable in CCD Region 2

SPHEN3

Mode_Reg(18)

High/Low

Special H Pattern Enable in CCD Region 3

SPHEN4

Mode_Reg(19)

High/Low

Special H Pattern Enable in CCD Region 4

NOTES

1The HBLKTOGx toggle positions reference the 12-bit HD counter.

2The SPHSTART0 and SPHSTART1 toggle positions reference the 8-bit LM counter.

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