PCD5008 datasheet(17/64 Pages) PHILIPS

17 / 64 page

1998 Jun 17

Philips Semiconductors

Product speciﬁcation

FLEX

™ Pager Decoder

PCD5008

8.4.4

CONFIGURATION PACKET (ID = 01H)

The configuration packet defines a number of different

configuration options for the PCD5008. The PCD5008

ignores this packet when decoding is enabled,

i.e. the ON bit in the control packet is set (Table 11).

OFD: oscillator frequency difference (Tables 4 and 5).

These bits represent the maximum frequency difference

between the 76.8 kHz oscillator (accounting for ageing,

temperature variation, manufacturing tolerance etc.) and

the worst case transmitter bit rate (specified in FLEX

™ as

±25 parts per million (ppm), see Section 15.3.1).

For example, if the transmitter tolerance is

±25 ppm and

the 76.8 kHz oscillator tolerance is

±140 ppm, the

transmitter-oscillator frequency difference is

±165 ppm

and OFD should be cleared (300 ppm max.). Value after

reset = 0. Note that configuring a smaller frequency

difference in this packet results in lower power

consumption due to higher receiver battery save ratios.

SME: synchronous mode enable (Table 5). When this bit

is set, a status packet is sent automatically whenever the

synchronous mode update (SMU) bit in the status packet

is set. This happens whenever a change occurs in the

synchronous mode (SM) status bit, which indicates that

the decoder is synchronized to a FLEX

™ data stream.

The host can use the SM bit in the status packet as an

in-range/out-of-range indication. Value after reset = 0.

MOT: maximum off time (Table 5). When this bit is set, the

PCD5008 assumes that there can be up to 1 minute

between transmitted frames on the paging system. When

this bit is clear, the PCD5008 assumes that there can be

up to 4 minutes between transmitted frames on the paging

system. This setting is determined by the service provider.

Value after reset = 0.

COD: clock output disable (Table 5). When this bit is clear,

a 38.4 kHz signal is output on the CLKOUT pin. When this

bit is set, the CLKOUT pin is driven HIGH. Note that

setting and clearing this bit can cause pulses on the

CLKOUT pin that are less than one half the 38.4 kHz

period. Also note that when the clock output is enabled, the

CLKOUT pin always outputs the 38.4 kHz signal even

when the PCD5008 is in reset. Value after reset = 0.

MTE: minute timer enable (Table 5). When this bit is set,

a status packet is sent at one minute intervals with the

minute time-out (MT) bit in the status packet set. When

this bit is clear, the internal 1-minute timer stops counting.

See Section 8.4.8 for details of 1-minute timer operation.

Value after reset = 0.

LBP: low battery polarity (Table 5). This bit defines the

polarity of the PCD5008’s LOBAT pin: When this bit is set,

a HIGH at input LOBAT represents a low battery condition.

The LB bit in the status packet is initialized to the inverse

(i.e. inactive) value of the LBP bit when the PCD5008 is

turned on (by setting the ON bit in the control packet).

When the PCD5008 is turned on, the first low battery

update in the status packet is sent to the host when a low

battery condition is detected on the LOBAT pin. Value

after reset = 0.

SP: signal polarity (Tables 5, 6 and 7). These bits set the

polarity of EXTS1 and EXTS0 input signals. The polarity of

the EXTS1 and EXTS0 bits is determined by the receiver

design. Value after reset = 0.

Table 4

Maximum oscillator frequency difference

OFD1

OFD0

FREQUENCY DIFFERENCE

(ppm)

±300

±150

±75

±0

Table 5

Conﬁguration packet bit assignments

BYTE

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

300000001

2000000

OFD1

OFD0

1000000

SP1

SP0

SME

MOT

COD

MTE

LBP

PCD5008 Datasheet(PDF) 17 Page - NXP Semiconductors

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