PCD5008 datasheet(25/64 Pages) PHILIPS

25 / 64 page

1998 Jun 17

Philips Semiconductors

Product speciﬁcation

FLEX

™ Pager Decoder

PCD5008

8.5.6.2

Receiver on setting packets (ID = 16H to 19H)

LBC: low battery check (Table 17). If this bit is set, the

PCD5008 checks the status of the LOBAT port just before

leaving this receiver sync setting state. Value after

reset = 0.

CLS: control line setting (Table 17). This is the value to be

output on the receiver control lines for this receiver

sync setting state. Value after reset = 0.

ST: step time (Table 17). This sets the waiting time, before

expecting good signals at EXTS1 and EXTS0 at the end of

the warm-up sequence, after turning decoding on.

The setting is in steps of 625

µs. Valid values are:

625

µs (ST = 01H) to 79.375 ms (ST = 7FH). Value after

reset = 01H.

LBC: low battery check (Table 18). If this bit is set, the

PCD5008 checks the status of the LOBAT port just before

leaving this receiver on state. Value after reset = 0.

CLS: control line setting (Table 18). This is the value to be

output on the receiver control lines (S0 to S7) for this

receiver on state. Value after reset = 0.

s: setting number, see Tables 16 and 18 for the s names

and values and location in the receiver on setting packet.

Table 16 s names and values

8.5.7

FORCING RECEIVER LINES (ID = 0FH)

This packet (Table 19) enables host control over the

receiver control line (S0 to S7) settings in all modes except

reset. In reset, the receiver control lines are high

impedance.

FRS: force receiver setting (Table 19). Setting a bit causes

the associated CLS bit in this packet to override the

internal receiver control settings on the corresponding

receiver control line. Clearing a bit returns control of the

corresponding receiver control line to the PCD5008. Value

after reset = 0.

CLS: control line setting (Table 19). This bit setting is

applied to the corresponding receiver control line if the

associated FRS bit is set in this packet. Value after

reset = 0.

SETTING NAME

0111

1600 sps sync

1000

3200 sps data

1001

1600 sps data

Table 17 3200 sps sync setting packet bit assignments

Table 18 Receiver on setting packet bit assignments

Table 19 Receiver line control packet bit assignments

BYTE

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

300010110

20000

LBC

000

CLS7

CLS6

CLS5

CLS4

CLS3

CLS2

CLS1

CLS0

ST6

ST5

ST4

ST3

ST2

ST1

ST0

BYTE

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

30001

20000

LBC

000

CLS7

CLS6

CLS5

CLS4

CLS3

CLS2

CLS1

CLS0

000000000

BYTE

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

300001111

200000000

FRS7

FRS6

FRS5

FRS4

FRS3

FRS2

FRS1

FRS0

CLS7

CLS6

CLS5

CLS4

CLS3

CLS2

CLS1

CLS0

PCD5008 Datasheet(PDF) 25 Page - NXP Semiconductors

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