PCD5008 datasheet(19/64 Pages) PHILIPS

19 / 64 page

1998 Jun 17

Philips Semiconductors

Product speciﬁcation

FLEX

™ Pager Decoder

PCD5008

8.4.7

CONTROL PACKET (ID = 02H)

The control packet defines a number of different control

bits for the PCD5008.

FF: force frame 0 to 7 (Table 11). When set, each of these

bits forces the PCD5008 to decode one of the FLEX

™

frames 0 to 7 irrespective of the system collapse value (for

details of collapse values see Section 8.6.2). For example,

if the system collapse causes the PCD5008 to decode

frames 0, 32, 64 and 96, setting FF2 causes the PCD5008

to also decode FLEX

™ frame 2. This may be used to

acquire transmitted time information. Value after reset = 0.

SPM: single phase mode (Table 11). When this bit is set,

the PCD5008 decodes only one of the transmitted phases.

When this bit is clear, the PCD5008 decodes all

transmitted phases. This value is determined by the

CAPCODE (Section 8.6). A change to this bit while the

PCD5008 is on does not take effect until the next block 0

of a frame. Value after reset = 0.

PS: phase select (Tables 10 and 11). When the SPM bit is

set, these bits define which phase the PCD5008 shall

decode. This value is determined by the CAPCODE

(Section 8.6). A change to these bits, while the PCD5008

is on, does not take effect until the next block 0 of a frame.

Value after reset = 0.

Table 10 Phase selection (PS bits)

SBI: send block information words (BIW) 2 to 4

(Table 11). When this bit is set, BIWs with time and date

information and BIWs received in error are sent to the host,

(Section 8.7.9). Value after reset = 0.

PS1

PS0

DECODED PHASE (BASED ON

FLEX

™ DATA RATE)

1600 bits/s 3200 bits/s 6400 bits/s

AAA

AAB

MTC: minute timer clear (Table 11). Setting this bit causes

the 1-minute timer to restart from 0 (Section 8.4.8).

ON: turn on decoder (Table 11). When this bit is set, the

PCD5008 decodes FLEX

™ signals. If this bit is cleared,

signal processing stops. However, to assure proper

operation, the PCD5008 requires that it be set into

asynchronous mode when turned off. To achieve that the

following sequence must be used:

1. Send control packet with ON bit clear (decoder off)

2. Send control packet with ON bit set (decoder on)

3. Send control packet with ON bit clear (decoder off).

Timing between these steps is specified below and is

measured from the positive edge of the last clock of one

packet to the positive edge of the last clock of the next

packet.

• The minimum time between steps 1 and 2 is the greater

of 2 ms or the programmed shut-down time.

The programmed shut-down time is the sum of all of the

times programmed in the used receiver shut-down

settings packets.

• There is no maximum time between steps 1 and 2

• The minimum time between steps 2 and 3 is 2 ms

• The maximum time between steps 2 and 3 is the

programmed warm-up time minus 2 ms.

The programmed warm-up time is the sum of all the

times programmed in the used receiver warm-up

settings packets.

8.4.8

OPERATING THE 1-MINUTE TIMER

The PCD5008 provides a 1-minute timer which allows the

host to implement a time-of-day function while maintaining

low-power operation. The 1-minute timer is enabled using

the MTE bit in the configuration packet (Section 8.4.4).

When the 1-minute timer is enabled, a status packet is

sent at 1-minute intervals with the MT bit set

(Section 8.4.9). When the MTE bit is clear, the internal

1-minute timer stops counting. When the host sends a

control packet with MTC bit set, the 1-minute timer restarts

from 0. This allows accurate setting of a time-of-day

function.

Table 11 Control packet bit assignments

BYTE

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

300000010

2FF7

FF6

FF5

FF4

FF3

FF2

FF1

FF0

SPM

PS1

PS0

0000

SBI

MTC

PCD5008 Datasheet(PDF) 19 Page - NXP Semiconductors

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