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VT6306 Datasheet(PDF) 19 Page - VIA Technologies, Inc. |
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VT6306 Datasheet(HTML) 19 Page - VIA Technologies, Inc. |
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19 / 59 page  We Connect We Connect We Connect We Connect Technologies,Inc. VT6306 PCI 1394a Host Controller Revision 1.16 July 19, 2002 -13- Register Overview Memory-Space Registers – Link Controller Offset Heading Default Acc 0 Version (OHCI 1.0 Mode) 0001 0000 RO Version (OHCI 1.1 Mode) 0001 0010 RO 4 -reserved- (GUID ROM) 0000 0000 — 8 Asynchronous Transmit Retries 0000 0000 RW C CSR Data 0000 0000 RW 10 CSR Compare Data 0000 0000 RW 14 CSR Control 8000 0000 RW 18 Configuration ROM Header 0000 0000 RW 1C 1394 Bus ID 3133 3934 RO 20 1394 Bus Options F000 0002 RW 24 Global Unique ID High 0000 0000 RW 28 Global Unique ID Low 0000 0000 RW 2C-33 -reserved- 00 — 34 Configuration ROM Map 0000 0000 RW 38 Posted Write Address Low 0000 0000 RO 3C Posted Write Address High 0000 0000 RO 40 Vendor ID 0000 0000 RO 44-4F -reserved- 00 — 50 HC Control Set 0000 0000 RW 54 HC Control Clear 0000 0000 RW 58-5F -reserved- 00 — 60-63 -reserved- 00 — 64 Self-ID Buffer Pointer 0000 0000 RW 68 Self-ID Count 0000 0000 RO 6C-6F -reserved- 00 — 70 Isoch Rcv Channel Mask High Set 0000 0000 RW 74 Isoch Rcv Channel Mask High Clr 0000 0000 RW 78 Isoch Rcv Channel Mask Low Set 0000 0000 RW 7C Isoch Rcv Channel Mask Low Clr 0000 0000 RW 80 Interrupt Event Set 0000 0000 RW 84 Interrupt Event Clear 0000 0000 RW 88 Interrupt Mask Set 0000 0000 RW 8C Interrupt Mask Clear 0000 0000 RW 90 Isoch Xmit Interrupt Event Set 0000 0000 RW 94 Isoch Xmit Interrupt Event Clear 0000 0000 RW 98 Isoch Xmit Interrupt Mask Set 0000 0000 RW 9C Isoch Xmit Interrupt Mask Clear 0000 0000 RW A0 Isoch Rcv Interrupt Event Set 0000 0000 RW A4 Isoch Rcv Interrupt Event Clear 0000 0000 RW A8 Isoch Rcv Interrupt Mask Set 0000 0000 RW AC Isoch Rcv Interrupt Mask Clear 0000 0000 RW Offset Heading Default Acc B3-B0 Initial Bandwidth Available 0000 1333 RW B7-B4 Initial Channels Available Hi FFFFFFFF RW BB-B8 Initial Channels Available Lo FFFFFFFF RW BC-DB -reserved- 00 — DC Fairness Control 0000 0000 RW E0 Link Control Set 0000 0000 RW E4 Link Control Clear 0000 0000 RW E8 Node ID 0000 0000 RW EC PHY Control 0000 0000 RW F0 Isochronous Cycle Timer 0000 0000 RW F4-FF -reserved- 00 — 100 Async Request Filter High Set 0000 0000 RW 104 Async Request Filter High Clear 0000 0000 RW 108 Async Request Filter Low Set 0000 0000 RW 10C Async Request Filter Low Clear 0000 0000 RW 110 Physical Request Filter High Set 0000 0000 RW 114 Physical Request Filter High Clear 0000 0000 RW 118 Physical Request Filter Low Set 0000 0000 RW 11C Physical Request Filter Low Clear 0000 0000 RW 120-123 Physical Upper Bound 0000 0000 RW 124-17F -reserved- 00 — 180 Async Request Xmit Context Set 0000 0000 RW 184 Async Request Xmit Context Clr 0000 0000 RW 18C Async Request Xmit Command Ptr 0000 0000 RW 1A0 Async Response Xmit Context Set 0000 0000 RW 1A4 Async Response Xmit Context Clr 0000 0000 RW 1AC Async Response Xmit Cmd Ptr 0000 0000 RW 1C0 Async Request Rcv Context Set 0000 0000 RW 1C4 Async Request Rcv Context Clr 0000 0000 RW 1CC Async Request Rcv Command Ptr 0000 0000 RW 1E0 Async Response Rcv Context Set 0000 0000 RW 1E4 Async Response Rcv Context Clr 0000 0000 RW 1EC Async Response Rcv Command Ptr 0000 0000 RW |
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