VT6306 datasheet(41/59 Pages) VIA

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VT6306 PCI 1394a Host Controller

Revision 1.16 July 19, 2002

-35-

PHY Registers

The PHY registers are accessed through the PHY Control

PHY Register Overview

Offset

0000b

Physical ID

0001b

Gap Count

IBR

RHB

0010b

Total Ports

Extended

0011b

Delay

Max Speed

0100b

Power Class

Jitter

Cont

0101b Multi Accel

Tout

Loop ISBR

0110b

-reserved-

0111b

Port Select

Page Select

1000b

1001b

1010b

1011b

1100b

1101b

1110b

1111b

PHY Register Bit Field Descriptions

Field

Bits Type Def Description

Physical_ID

The address of this node determined

during self-identification. A value

of 63 indicates a malconfigured bus

where the link must not transmit any

packets.

A setting of one indicates that this

node is the root.

Cable Power status.

RHB

Root hold-off bit. A setting of one

instructs the chip to attempt to

become the root during the next tree

identification process.

IBR

Initiate bus reset. A setting of one

instructs the chip to initiate a bus

reset

immediately

(without

arbitration).

This causes assertion

of the reset state for 166 us and is

self-clearing.

Gap Count

3Fh Used to configure the arbitration

timer setting in order to optimize

gap times according to the topology

of the bus.

Extended

111 Constant value of seven

Total Ports

011 Three ports

Max Speed

010 Supports

98.304,

196.608,

and

393.216 Mbit/s

Delay

Worse case repeater delay = 144 ns

Link Control

Link Control.

Cleared or set by

software to control the value of the

L bit transmitted in the node’s Self-

ID packet 0.

PHY Register Bit Field Descriptions (continued)

Contender

CMC

Contender.

Cleared

set

software to control the value of the

C bit transmitted in the first self-ID

packet.

Power Class

Pins

[0:2]

Power class. This information will

be copied to bits 21-23 of the first

self-ID packet.

Jitter

Repeater delay; 20ns variation max

Watchdog

enable.

Controls

whether loop, power fail, and

timeout interrupts are indicated to

the link when the link is in sleep.

Also determines whether interrupts

are indicated to the internal link

when resume operations start from

any port.

ISBR

Initiate short (arbitrated) bus reset.

A write of one to this bit instructs

the chip to arbitrate and issue a

short bus reset.

This bit is self-

clearing.

Loop

Loop detect. A write of one to this

bit clears it to zero.

Power Fail

Cable power failure detect. Set to

one when the PS bit changes from

one to zero. A write of one to this

bit clears it to zero.

Timeout

Arbitration state machine timeout.

A write of one to this bit clears it

to zero.

Port Event

Port event detect. The chip sets

this bit to one if any of connected,

Bias, Disabled or Fault change for

a port whose Int_enable bit is one.

The chip also sets this bit to one if

resume operations commence for

any port and Resume_int is one. A

write of one to this bit clears it to

zero.

Enable

Acceleration

Enable

arbitration

acceleration.

When set to one, the chip must use

the enhancements specification in

IEEE P1394a 4.0.

Enable Multi

Enable

multi-speed

packet

concatenation.

Page Select

000

Selects which of eight possible

PHY register pages are accessible

through

the

window

PHY

1111b, inclusive.

Port Select

0000 If the page selected by Page_select

presents per port information, this

field selects which port’s registers

are accessible through the window

at PHY register addresses 1000b

through 1111b, inclusive.

VT6306 Datasheet(PDF) 41 Page - VIA Technologies, Inc.

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