ATMEGA3290P datasheet(21/360 Pages) ATMEL

21 / 360 page

8021A–AVR–12/06

ATmega329P/3290P

Figure 6-2.

Data Memory Map

6.3.1

Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk

CPU cycles as described in Figure 6-3.

Figure 6-3.

On-chip Data SRAM Access Cycles

6.4

EEPROM Data Memory

The ATmega329P/3290P contains 1K bytes of data EEPROM memory. It is organized as a sep-

arate data space, in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the

CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM

Data Register, and the EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see

page 309, page 315, and page 298 respectively.

6.4.1

EEPROM Write During Power-down Sleep Mode

When entering Power-down sleep mode while an EEPROM write operation is active, the

EEPROM write operation will continue, and will complete before the Write Access time has

passed. However, when the write operation is completed, the clock continues running, and as a

consequence, the device does not enter Power-down entirely. It is therefore recommended to

verify that the EEPROM write operation is completed before entering Power-down.

32 Registers

64 I/O Registers

Internal SRAM

(2048 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x08FF

0x0060 - 0x00FF

Data Memory

160 Ext I/O Reg.

0x0100

clk

Data

Address

Address valid

Compute Address

CPU

Memory Access Instruction

Next Instruction

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