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DLPC964 Datasheet(PDF) 32 Page - Texas Instruments

Part # DLPC964
Description  DLPC964 Digital Micromirror Device Controller
PDF  77 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DLPC964 Datasheet(HTML) 32 Page - Texas Instruments

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Table 6-9. Communication Registers (continued)
ADDRESS
REGISTER NAME
DESCRIPTION
SIZE
0x40000100
SSF_FPGA_RST
DLPC964 Reset
32
0x40000200
HSS_RESET
Aurora Reset
32
0x40000204
HSS_CHANNEL_STATUS
Aurora 64B/66B Input Channel Status
32
0x40000208
HSS_LANE_STATUS
Aurora 64B/66B Input Lane Status
32
0x4000020C
HSS_CH0_SOFTERROR_COUNT
Aurora 64B/66B Channel 0 Soft Error Count
32
0x40000210
HSS_CH1_SOFTERROR_COUNT
Aurora 64B/66B Channel 1 Soft Error Count
32
0x40000214
HSS_CH2_SOFTERROR_COUNT
Aurora 64B/66B Channel 2 Soft Error Count
32
0x40000218
HSS_CH3_SOFTERROR_COUNT
Aurora 64B/66B Channel 3 Soft Error Count
32
0x4000021C
HSS_SOFTERROR_COUNT_RESET
Reset Soft Error Count
32
0x40000300
BPG_FEN
Bitplane Pattern Generator Enable
32
0x40000304
BPG_CFG_BLK_ACTIVE
Bitplane Pattern Generator Active Block Configuration
32
0x40000308
BPG_CFG_CTRL
Bitplane Pattern Generator Controls
32
0x40000404
HSI_CH0DMDDAT_GTCTRL
HSSI channel 0 DMD data GT cell control
32
0x40000408
HSI_CH0DMDCLK_GTCTRL
HSSI channel 0 DMD clock GT cell control
32
0x4000040C
HSI_CH1DMDDAT_GTCTRL
HSSI channel 1 DMD data GT cell control
32
0x40000410
HSI_CH1DMDCLK_GTCTRL
HSSI channel 1 DMD clock GT cell control
32
0x40000414
HSI_CH2DMDDAT_GTCTRL
HSSI channel 2 DMD data GT cell control
32
0x40000418
HSI_CH2DMDCLK_GTCTRL
HSSI channel 2 DMD clock GT cell control
32
0x4000041C
HSI_CH3DMDDAT_GTCTRL
HSSI channel 3 DMD data GT cell control
32
0x40000420
HSI_CH3DMDCLK_GTCTRL
HSSI channel 3 DMD clock GT cell control
32
0x40000424
HSI_VCM_VAL
HSSI DMD Vcm Value
32
0x4000051C
TEST_DMD_ID
DMD ID
32
0x40000520
TEST_DMD_FUSE1
DMD Fuse Group 1
32
0x40000524
TEST_DMD_FUSE2
DMD Fuse Group 2
32
0x40000528
TEST_DMD_FUSE3
DMD Fuse Group 3
32
0x4000052C
TEST_DMD_FUSE4
DMD Fuse Group 4
32
Register Definitions
The following designations are used throughout this section of the document:
• R—Designates read only
• W—Designates write only
• R/W—Designates read and write
• S—Designates status of register
• I —Designates interrupt only
• P—Designates pulse only
6.5.1.1 FPGA_INTERRUPT_STATUS Register
The FPGA_INTERRUPT_STATUS register contains the status for the Watchdog timeout and the four Aurora
64B/66B Channels Hard Error status. A '1' can be written to these registers to clear their status.
Table 6-10. FPGA_INTERRUPT_STATUS Register
Bit(s)
Description
Reset
Type
Notes
0
Fieldname: Reserved
0x0
1
SPARE
0x0
DLPC964
DLPS167 – MARCH 2024
www.ti.com
32
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Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: DLPC964



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