DLPC964 datasheet(39/77 Pages) TI1

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Table 6-21. PRBS7_MACRO3_TEST_RESULT Register (continued)

Bit(s)

Description

Reset

Type

Notes

Fieldname: PRBS7_M3LN1_TEST_RESULT_FLD

0x0

'1' = DMD Macro 3 lane 1 test passed

'0' = test failed

Fieldname: PRBS7_M3LN2_TEST_RESULT_FLD

0x0

'1' = DMD Macro 3 lane 2 test passed

'0' = test failed

Fieldname: PRBS7_M3LN3_TEST_RESULT_FLD

0x0

'1' = DMD Macro 3 lane 3 test passed

'0' = test failed

Fieldname: PRBS7_M3LN4_TEST_RESULT_FLD

0x0

'1' = DMD Macro 3 lane 4 test passed

'0' = test failed

Fieldname: PRBS7_M3LN5_TEST_RESULT_FLD

0x0

'1' = DMD Macro 3 lane 5 test passed

'0' = test failed

Fieldname: PRBS7_M3LN6_TEST_RESULT_FLD

0x0

'1' = DMD Macro 3 lane 6 test passed

'0' = test failed

Fieldname: PRBS7_M3LN7_TEST_RESULT_FLD

0x0

'1' = DMD Macro 3 lane 7 test passed

'0' = test failed

31:8

UNUSED

0x0

6.5.1.13 PRBS7_TEST_CONTROL Register

The PRBS7_TEST_CONTROL Register controls the PRBS7 Testing available on the DMD High Speed

Interface. The duration of the test for each lane can be set, which DMD channel(s) are tested, and which

lanes within the selected DMD channel(s) are tested.

Table 6-22. PRBS7_TEST_CONTROL Register

Bit(s)

Description

Reset

Type

Notes

15:0

Fieldname: PRBS7_TESTDURATION_FLD

0x0

r/w

PRBS7 run test time for each lane.

LSB = 1 ms.

Default to zero = 10ms.

Fieldname: PRBS7_DMDCH0_SELECT_FLD

0x1

r/w

1' = enable PRBS7 test running on DMD channel 0 (use lane enable to select specific lane)

Fieldname: PRBS7_DMDCH1_SELECT_FLD

0x1

r/w

1' = enable PRBS7 test running on DMD channel 1 (use lane enable to select specific lane)

Fieldname: PRBS7_DMDCH2_SELECT_FLD

0x1

r/w

1' = enable PRBS7 test running on DMD channel 2 (use lane enable to select specific lane)

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DLPC964

DLPS167 – MARCH 2024

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