DLPC964 datasheet(59/77 Pages) TI1

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be taken by the APPS FPGA to avoid overrunning these two buffers. Refer to Figure 7-5. After completing

the current Aurora data transfer of block data and asserting the DMDLOAD_REQ signal, the APPS FPGA

must wait for the de-assertion of BLKLOADZ by the DLPC964 Controller (i.e. BLKLOADZ transition from low

to high) before starting the next block data transfer. De-assertion of BLKLOADZ indicates that the DLPC964

Controller has completed the DMD data loading operation for previous block, and a data buffer is freed up for

accepting a new data block from the Aurora interface. The buffer will be overrun and data will be incorrectly

loaded to the DMD if the APPS FPGA does not synchronize the Aurora block data transfer with BLKLOADZ

signal de-assertion.

• It is not necessary for the APPS FPGA to immediately assert DMDLOAD_REQ after sending a DMD data

block. The APPS FPGA may send the DLPC964 Controller a DMD data block and then delay the assertion of

DMDLOAD_REQ until the system is ready for the DMD be loaded. Figure 7-6 describes this operation.

Figure 7-5. End of Block DMDLOAD_REQ Assertion Followed by New Block Control Word Waveform

1. APPS FPGA user logic asserts DMDLOAD_REQ immediately after the completion of current block data

transmission on all four Aurora data interfaces.

2. DLPC964 Controller de-asserts BLKLOADZ, indicating completion of the data loading operation for the

previous DMD block.

3. APPS FPGA user logics detects the de-assertion of BLKLOADZ and sends a new Block Control Word on

Aurora Channel 0 User-K Port for the next block data.

4. APPS FPGA user logics sending data for next block.

5. BLKLOADZ is asserted low by the DLPC964 Controller, indicating the data loading operation for current

block triggered by DMDLOAD_REQ occurred at 1.

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DLPC964

DLPS167 – MARCH 2024

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DLPC964 Datasheet(PDF) 59 Page - Texas Instruments