DLPC964 datasheet(34/77 Pages) TI1

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Table 6-11. FPGA_INTERRUPT_ENABLE_CONTROL Register (continued)

Bit(s)

Description

Reset

Type

Notes

Fieldname: HSS_CH1_HARD_ERROR_INT_EN_FLD

0x0

'1': allow Input Aurora Channel 1 hard error to assert Controller interrupt output.

If this bit and FPGA_INTERRUPT_STATUS register bit 4 are set, the Controller interrupt output

would be asserted

Fieldname: HSS_CH2_HARD_ERROR_INT_EN_FLD

0x0

'1': allow Input Aurora Channel 2 hard error to assert Controller interrupt output.

If this bit and FPGA_INTERRUPT_STATUS register bit 5 are set, the Controller interrupt output

would be asserted

Fieldname: HSS_CH3_HARD_ERROR_INT_EN_FLD

0x0

'1': allow Input Aurora Channel 3 hard error to assert Controller interrupt output.

If this bit and FPGA_INTERRUPT_STATUS register bit 6 are set, the Controller interrupt output

would be asserted

SPARE

0x0

31:8

UNUSED

0x0

6.5.1.3 FPGA_MAIN_STATUS Register

The FPGA_MAIN_STATUS Register contains the status for the DLPC964 PLL Lock, DMD POWERGOOD, DMD

Parked Status, and DMD High Speed Interface power status. This register is a read only register, and status bits

can only be set/cleared by the DLPC964.

Table 6-12. FPGA_MAIN_STATUS Register

Bit(s)

Description

Reset

Type

Notes

Fieldname: MAIN_STATUS_PLL_LOCKED_FLD

0x0

Read-only status

1: DLPC964 PLL locked

0: not locked

Fieldname: MAIN_STATUS_DMDPWRGOOD_FLD

0x0

Read-only status

1: DMD power good from external regulator

0: DMD power not good from external regulator

Fieldname: MAIN_STATUS_RSCDRC_DMDPARKED_FLD

0x0

Read-only status

1: DMD is parked

0: DMD is not parked

Fieldname: MAIN_STATUS_HSIFPWRON_FLD

0x0

Read-only status.

1: DMD high speed interface power on

0: DMD high speed interface power off

31:4

UNUSED

0x0

DLPC964

DLPS167 – MARCH 2024

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