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DLPC964 Datasheet(PDF) 8 Page - Texas Instruments |
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DLPC964 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 77 page  Table 4-1. Pin Functions (continued) PIN I/O TYPE(1) ACTIVE (HI OR LO) CLOCK SYSTEM DESCRIPTION NAME NO. TDO_0 AA25 LVCMOS18_O — — JTAG Data out of DLPC964. Connects to JTAG return TDO on JTAG connector TDI_0 AB25 LVCMOS18_I — — JTAG Data into DLPC964. Connects to JTAG input TDI on JTAG connector TMS_0 W25 LVCMOS18_I — — JTAG Data. Connects to JTAG TMS on JTAG connector TCK_0 Y25 LVCMOS18_I — — JTAG Clock. Connects to JTAG TCK on JTAG connector INIT_B_0 T10 LVCMOS18_O — — DLPC964 Configuration. Pull up to 1.8V with a 4.7KΩ resistor. CFGBVS_0 U10 LVCMOS18_I — — DLPC964 Configuration. Connect to GND. PROGRAM_B_0 V10 LVCMOS18_O — — DLPC964 Configuration. Pull up to 1.8V with a 4.7KΩ resistor. DONE_0 AB10 LVCMOS18_O HI — DLPC964 Configuration. Pull up to 1.8V with a 330Ω resistor. K_DATA[0] K22 LVDCI_18_O — CLK_K Bit 64 of user_k_tdata[] K_DATA[1] K23 LVDCI_18_O — CLK_K Bit 65 of user_k_tdata[] K_DATA[2] M23 LVDCI_18_O — CLK_K Bit 66 of user_k_tdata[] K_VALID K24 LVDCI_18_O — CLK_K K_DATA[3] L23 LVDCI_18_O — CLK_K Bit 67 of user_k_tdata[] CLK_K L24 LVDCI_18_I — — K_DATA Clock input (156.25MHz) K_DATA[4] L25 LVDCI_18_O — CLK_K Bit 68 of user_k_tdata[] FAN_PWM N22 LVDCI_18_O — — To DLPC964 Controller Fan connector TESTMUX0 AE11 LVDCI_18_O — — No connect. For access to test point output route to test via. TESTMUX1 AE13 LVDCI_18_O — — No connect. For access to test point output route to test via. TESTMUX2 AE14 LVDCI_18_O — — No connect. For access to test point output route to test via. TESTMUX3 AF10 LVDCI_18_O — — No connect. For access to test point output route to test via. TESTMUX4 AF11 LVDCI_18_O — — No connect. For access to test point output route to test via. TESTMUX5 AF13 LVDCI_18_O — — No connect. For access to test point output route to test via. TESTMUX6 AF14 LVDCI_18_O — — No connect. For access to test point output route to test via. TESTMUX7 AG10 LVDCI_18_O — — No connect. For access to test point output route to test via. TESTMUX8 AG11 LVDCI_18_O — — No connect. For access to test point output route to test via. TESTMUX9 AG12 LVDCI_18_O — — No connect. For access to test point output route to test via. TESTMUX10 AG13 LVDCI_18_O — — No connect. For access to test point output route to test via. TESTMUX11 AH12 LVDCI_18_O — — No connect. For access to test point output route to test via. TESTMUX12 AH13 LVDCI_18_O — — No connect. For access to test point output route to test via. TESTMUX13 AH14 LVDCI_18_O — — No connect. For access to test point output route to test via. TESTMUX14 AJ9 LVDCI_18_O — — No connect. For access to test point output route to test via. TESTMUX15 AJ10 LVDCI_18_O — — No connect. For access to test point output route to test via. VN_0 Y17 — — — Connect to GND. VP_0 W18 — — — Connect to GND. VREFN_0 W17 — — — Connect to GND. VREFP_0 Y18 — — — Connect to GND. DLPC964 DLPS167 – MARCH 2024 www.ti.com 8 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: DLPC964 |
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