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56F8014 Datasheet(PDF) 101 Page - Freescale Semiconductor, Inc |
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56F8014 Datasheet(HTML) 101 Page - Freescale Semiconductor, Inc |
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101 / 125 page  Serial Peripheral Interface (SPI) Timing 56F8014 Technical Data, Rev. 9 Freescale Semiconductor 101 Preliminary 10.9 Serial Peripheral Interface (SPI) Timing Table 10-14 SPI Timing1 1. Parameters listed are guaranteed by design. Characteristic Symbol Min Max Unit See Figure Cycle time Master Slave tC 125 62.5 — — ns ns 10-7, 10-8, 10-9, 10-10 Enable lead time Master Slave tELD — 31 — — ns ns 10-10 Enable lag time Master Slave tELG — 125 — — ns ns 10-10 Clock (SCK) high time Master Slave tCH 50 31 — — ns ns 10-7, 10-8, 10-9, 10-10 Clock (SCK) low time Master Slave tCL 50 31 — — ns ns 10-10 Data set-up time required for inputs Master Slave tDS 20 0 — — ns ns 10-7, 10-8, 10-9, 10-10 Data hold time required for inputs Master Slave tDH 0 2 — — ns ns 10-7, 10-8, 10-9, 10-10 Access time (time to data active from high-impedance state) Slave tA 4.8 15 ns 10-10 Disable time (hold time to high-impedance state) Slave tD 3.7 15.2 ns 10-10 Data Valid for outputs Master Slave (after enable edge) tDV — — 4.5 20.4 ns ns 10-7, 10-8, 10-9, 10-10 Data invalid Master Slave tDI 0 0 — — ns ns 10-7, 10-8, 10-9, 10-10 Rise time Master Slave tR — — 11.5 10.0 ns ns 10-7, 10-8, 10-9, 10-10 Fall time Master Slave tF — — 9.7 9.0 ns ns 10-7, 10-8, 10-9, 10-10 |
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