56F8014 datasheet(2/125 Pages) FREESCALE

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56F8014 Technical Data, Rev. 9

Freescale Semiconductor

Preliminary

Document Revision History

Version History

Description of Change

Rev 0

Initial release

Rev 1

Updates to Part 10, Specifications,

Table 10-1, added maximum clamp current, per pin

Table 10-11, clarified variation over temperature table and graph

Table 10-15, added LIN slave timing

Rev 2

Added alternate pins to Figure 11-1 and Table 11-1.

Rev 3

Corrected bit selects in Timer Channel 3 Input (TC3_INP) bit 9, Section 6.3.1.7, clarified

Section 1.4.1, and simplified notes in Table 10-9,

Rev 4

Added clarification on sync inputs in Section 1.4.1, added voltage difference specification to

Table 10-1 and Table 10-4, deleted formula for Ambient Operating Temperature in Table 10-4,

and a note for pin group 3, corrected Table 8-1, error in Port C peripheral function configuration,

updated notes in Table 10-9. Added RoHs and “pb-free” language to back cover.

Rev 5

Updates to Section 10

Table 10-5, corrected max values for ADC Input Current High and Low; corrected typ value for

pull-up disabled Digital Input Current Low (a)

Table 10-6, corrected typ and added max values for Standby > Stop and Powerdown modes

Table 10-7, corrected min value for Low-Voltage Interrupt for 3.3V

Table 10-11, corrected typ and max values and units for PLL lock time

Table 10-12, corrected typ values for Relaxation Oscillator output frequency and variation over

temperature (also increased temp range to 150 degreesC) and added variation over

temperature from 0—105 degreesC

Updated Figure 10-5

Table 10-19, updated max values for Integral Non-Linearity full input signal range, Negative

Differential Non-Linearity, ADC internal clock, Offset Voltage Internal Ref, Gain Error and Offset

Voltage External Ref; updated typ values for Negative Differential Non-Linearity, Offset Voltage

Internal Ref, Gain Error and Offset Voltage External Ref; added new min values and corrected

typ values for Signal-to-noise ratio, Total Harmonic Distortion, Spurious Free Dynamic Range,

Signal-to-noise plus distortion, Effective Number of Bits

Rev 6

Added details to Section 1. Clarified language in State During Reset column in Table 2-3;

corrected flash data retention temperature in Table 10-4; moved input current high/low

toTable 10-19 and location of footnotes in Table 10-5; reorganized Table 10-19; clarified title of

Figure 10-1.

Rev. 7

• In Table 10-4, added an entry for flash data retention with less than 100 program/erase

cycles (minimum 20 years).

•In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz.

•In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode

from 400kHz to 200kHz.

Rev. 8

In Table 10-19, changed the maximum ADC internal clock frequency from 8MHz to 5.33MHz.

56F8014 Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc

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