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DSP56853 Datasheet(PDF) 33 Page - Freescale Semiconductor, Inc |
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DSP56853 Datasheet(HTML) 33 Page - Freescale Semiconductor, Inc |
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33 / 60 page ![]() Reset, Stop, Wait, Mode Select, and Interrupt Timing 56853 Technical Data, Rev. 6 Freescale Semiconductor 33 4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing RD Deasserted to Address Invalid tRDA - 0.44 0.00 RWSH ns Address Valid to RD Deasserted tARDD -2.07 1.00 RWSS,RWS ns Valid Input Data Hold after RD Deasserted tDRD 0.00 N/A1 — ns RD Assertion Width tRD -1.34 1.00 RWS ns Address Valid to Input Data Valid tAD -10.27 1.00 RWSS,RWS ns -13.5 1.19 Address Valid to RD Asserted tARDA - 0.94 0.00 RWSS ns RD Asserted to Input Data Valid tRDD -9.53 1.00 RWSS,RWS ns -12.64 1.19 WR Deasserted to RD Asserted tWRRD -0.75 0.25 WWSH,RWSS ns RD Deasserted to RD Asserted tRDRD -0.162 0.00 RWSS,RWSH ns WR Deasserted to WR Asserted tWRWR WWS=0 -0.44 0.75 WWSS, WWSH ns WWS>0 -0.11 1.00 RD Deasserted to WR Asserted tRDWR 0.14 0.50 MDAR, BMDAR, RWSH, WWSS ns -0.57 0.69 1. N/A since device captures data before it deasserts RD 2. If RWSS = RWSH = 0, RD does not deassert during back-to-back reads and D=0.00 should be used. Table 4-8 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2 Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz Characteristic Symbol Min Max Unit See Figure RESET Assertion to Address, Data and Control Signals High Impedance tRAZ — 11 ns 4-11 Minimum RESET Assertion Duration3 tRA 30 — ns 4-11 RESET Deassertion to First External Address Output tRDA — 120T ns 4-11 Edge-sensitive Interrupt Request Width tIRW 1T + 3 — ns 4-12 Table 4-7 External Memory Interface Timing (Continued) Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98 V, VDDIO = VDDA = 3.0–3.6V, TA = –40× to +120×C, CL £ 50pF, P = 8.333ns Characteristic Symbol Wait States Configuration DM Wait States Controls Unit |
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