DSP56853 datasheet(34/60 Pages) FREESCALE

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56853 Technical Data, Rev. 6

Freescale Semiconductor

IRQA, IRQB Assertion to External Data Memory

Access Out Valid, caused by first instruction execution

in the interrupt service routine

tIDM

18T

—

4-13

tIDM -FAST

14T

—

IRQA, IRQB Assertion to General Purpose Output

Valid, caused by first instruction execution in the

interrupt service routine

tIG

18T

—

4-13

tIG -FAST

14T

—

IRQA Low to First Valid Interrupt Vector Address Out

recovery from Wait State4

tIRI

22T

—

4-14

tIRI -FAST

18T

—

Delay from IRQA Assertion (exiting Stop) to External

Data Memory5

tIW

1.5T

—

4-15

Delay from IRQA Assertion (exiting Wait) to External

Data Memory

Fast6

Normal7

tIF

18T

22ET

—

4-15

RSTO pulse width8

normal operation

internal reset mode

tRSTO

128ET

8ET

—

4-16

In the formulas, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.

Parameters listed are guaranteed by design.

At reset, the PLL is disabled and bypassed. The part is then put into Run mode and tclk assumes the period of the source

clock, txtal, textal or tosc.

The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is

not the minimum required so that the IRQA interrupt is accepted.

The interrupt instruction fetch is visible on the pins only in Mode 3.

Fast stop mode:

Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is

requested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes

one less cycle and tclk will continue same value it had before stop mode was entered.

Normal stop mode:

As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master

clock, recovery will take an extra cycle (to restart the clock), and tclk will resume at the input clock source rate.

ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns.

Table 4-8 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2 (Continued)

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic

Symbol

Min

Max

Unit

See Figure

DSP56853 Datasheet(PDF) 34 Page - Freescale Semiconductor, Inc

DSP56853 Datasheet(HTML) 34 Page - Freescale Semiconductor, Inc

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