DSP56853 datasheet(46/60 Pages) FREESCALE

46 / 60 page

56853 Technical Data, Rev. 6

Freescale Semiconductor

Delay from SCK high to SC2 (wl) high - Slave5

tTFSWHS

-1

—

Delay from SC0 high to SC1 (bl) high - Slave5

tRFSBHS

-1

—

Delay from SC0 high to SC1 (wl) high - Slave5

tRFSWHS

-1

—

Delay from SCK high to SC2 (bl) low - Slave5

tTFSBLS

-29

—

Delay from SCK high to SC2 (wl) low - Slave5

tTFSWLS

-29

—

Delay from SC0 high to SC1 (bl) low - Slave5

tRFSBLS

-29

—

Delay from SC0 high to SC1 (wl) low - Slave5

tRFSWLS

-29

—

SCK high to STD enable from high impedance - Slave

tTXES

—

SCK high to STD valid - Slave

tTXVS

—

SC2 high to STD enable from high impedance (first bit) - Slave

tFTXES

—

SC2 high to STD valid (first bit) - Slave

tFTXVS

—

SCK high to STD not valid - Slave

tTXNVS

—

SCK high to STD high impedance - Slave

tTXHIS

—

SRD Setup time before SC0 low - Slave

tSS

—

SRD Hold time after SC0 low - Slave

tHS

—

Synchronous Operation (in addition to standard external clock parameters)

SRD Setup time before SCK low - Slave

tTSS

—

SRD Hold time after SCK low - Slave

tTHS

—

1. Slave mode is externally generated clocks and frame syncs

2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part.

3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)

and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync

have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in

the tables and in the figures.

4. 50 percent duty cycle

5. bl = bit length; wl = word length

Table 4-13 ESSI Slave Mode1 Switching Characteristics (Continued)

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Parameter

Symbol

Min

Typ

Max

Units

DSP56853 Datasheet(PDF) 46 Page - Freescale Semiconductor, Inc

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