56F8366 datasheet(128/184 Pages) FREESCALE

128 / 184 page

56F8366 Technical Data, Rev. 6

128

Freescale Semiconductor

Preliminary

6.5.9

Peripheral Clock Enable Register (SIM_PCE)

The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power

savings feature. The clocks can be individually controlled for each peripheral on the chip.

Figure 6-13 Peripheral Clock Enable Register (SIM_PCE)

6.5.9.1

External Memory Interface Enable (EMI)—Bit 15

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.2

Analog-to-Digital Converter B Enable (ADCB)—Bit 14

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.3

Analog-to-Digital Converter A Enable (ADCA)—Bit 13

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.4

FlexCAN Enable (CAN)—Bit 12

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

6.5.9.5

Decoder 1 Enable (DEC1)—Bit 11

Each bit controls clocks to the indicated peripheral.

•

1 = Clocks are enabled

•

0 = The clock is not provided to the peripheral (the peripheral is disabled)

Base + $C

Read

EMI

ADCB ADCA CAN DEC1 DEC0 TMRD TMRC TMRB TMRA SCI 1 SCI 0

SPI 1

SPI 0

PWMB

PWMA

Write

RESET

56F8366 Datasheet(PDF) 128 Page - Freescale Semiconductor, Inc

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