SC28L194 datasheet(27/52 Pages) PHILIPS

27 / 52 page

Philips Semiconductors

Preliminary specification

SC28L194

Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

Table 29.

IVR - Interrupt Vector Register

Bits 7:0

8 data bits of the Interrupt Vector (IVR)

The IVR contains the byte that will be placed on the data bus during

an IACKN cycle when the GCCR bits (2:1) are set to binary ‘01’.

This is the unmodified form of the interrupt vector.

Table 30.

Modification of the IVR

Bits 7:5

Bits 4:3

Bits 2:0

Always contains

bits (7:5) of the IVR

Will be replaced

with current

interrupt type if IVC

field of GCCR = 3

Replaced with

interrupting channel

number if IVC field of

GCCR > 1

The table above indicates how the IVR may be modified by the

interrupting source. The modification of the IVR as it is presented to

the data bus during an IACK cycle is controlled by the setting of the

bits (2:1) in the GCCR (Global Chip Configuration Register)

Table 31.

GICR - Global Interrupting Channel

Bits 7:3

Bits 2:0

Reserved

Channel code

000 = a

001 = b

010 = c

011 = d

A register associated with the interrupting channel as defined in the

CIR. It contains the interrupting channel code for all interrupts.

Table 32.

GIBCR - Global Interrupting Byte Count

Bits 7:4

Bits 3:0

Reserved

Channel byte count code

0000 = 1 AND RxRDY status set for RxFIFO

0000 = 1 AND TxRDY status set for TxD

0001 = 2

0010 = 3

1111 = 16

A register associated with the interrupting channel as defined in the

CIR. Its numerical value equals the number of bytes minus 1

(count - 1) ready for transfer to the transmitter or transfer from the

receiver. It is undefined for other types of interrupts

Table 33.

Global Interrupting Type Register

Bit 7:6

Bit 5

Bit 4:3

Bit 2:0

Receiver Interrupt

Transmitter Interrupt

Reserved

Other types

0x - not receiver

10 - with receive errors

11 - w/o receive errors

0 - not transmitter

1 - transmitter interrupt

read b’00

000 - not “other” type

001 - Change of State

010 - Address Recognition Event

011 - Xon/Xoff status

100 - Not used

101 - Break Change

11x - do not occur

A register associated with the interrupting channel as defined in the

CIR. It contains the type of interrupt code for all interrupts.

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