SC28L194 datasheet(30/52 Pages) PHILIPS

30 / 52 page

Philips Semiconductors

Preliminary specification

SC28L194

Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

The registers of the SC28L194 are partitioned into two groups: those

used in controlling data channels and those used in handling the

actual data flow and status. Below is shown the general

configuration of all the register addressed. The “Register Map

Summary” shows the configuration of the lower four bits of the

address that is the same for the individual UARTs. It also shows the

addresses for the several in the address space of UART A and

UART B that apply to the total chip configuration. The “Register Map

Detail” shows the use of every address in the 8-bit address space.

NOTE: The register maps for channels A and B (UARTs A and B)

contain some control registers that configure the entire chip. These

are denoted by a

♣ symbol

Table 43.

Summary Register Map, Control

Address (hex) ccc = channel

Acronym

Read / Write

Page

0ccc 0000 (x00)

Mode Register 0 MR0a

MR0

R/W

0ccc 0001 (x01)

Mode Register 1 MR1a

MR1

R/W

0ccc 0010 (x02)

I/O Port Configuration Reg a I/OPCRa

IOPCR

R/W

0ccc 0011 (x03)

Bid Control, Break Change

BCRBRK

R/W

0ccc 0100 (x04)

Bid Control, Change of State

BCRCOS

R/W

0ccc 0110 (x06)

Bid Control, Xon/Xoff

BCRX

R/W

0ccc 0111 (x07)

Bid Control, Address recognition

BCRA

R/W

0ccc 1000 (x08)

Xon Character Register

XonCR

R/W

0ccc 1001 (x09)

Xoff Character Register

XoffCR

R/W

0ccc 1010 (x0A)

Address Recognition Character

ARCR

R/W

0ccc 1100 (x0C)

Receiver Clock Select Register

RxCSR

R/W

0000 1101 (x0D)

♣ Test Register

Reserved, set to 0

0ccc 1110 (x0E)

Transmitter Clock Select Register

TxCSR

R/W

0000 1111 (x0F)

♣ Global Chip Configuration Register

GCCR

R/W

0001 1011 (x1B)

♣ Interrupt Control Register

ICR

R/W

0001 1101 (x1D)

♣ Watch-dog Timer Run Control

WDTRCR

R/W

0001 1111 (x1F)

♣ Interrupt Vector Register

IVR

R/W

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