SC28L194 datasheet(36/52 Pages) PHILIPS

36 / 52 page

Philips Semiconductors

Preliminary specification

SC28L194

Quad UART for 3.3V and 5V supply voltage

1998 Sep 21

RESET CONDITIONS

Device Configuration after Hardware Reset

or CRa cmd=x1F

Cleared registers:

Channel Status Registers (SR)

Channel Interrupt Status Registers (ISR)

Channel Interrupt Mask Registers (IMR)

Channel Interrupt Xon Status Register (XISR)

Interrupt Control Register (ICR)

Global Configuration Control Register (GCCR)

Hence the device enters the asynchronous bus cycling mode.

Current Interrupt Register (CIR)

BRG Timer Run Control Register (BRGTCR)

Watch-dog Timer Run Control Register (WDTRCR)

Channel Input/Output Port Configuration Registers (I/OPCR)

Hence all I/O pins have direction = Input after reset

BRG Counter/Timer Registers

Clears Modes for:

Power down

Test modes

Input Port Changed bits

Gang write to Xon or Xoff

Xon/Xoff/Address detection

Receiver error status

Disables:

Transmitters

Receivers

Interrupts, current and future

Halts:

BRG Counters

Bus cycle in progress (hardware RESET only)

Limitations:

Minimum RESETN pin pulse width is 10 SClk cycles after Vcc

reaches operational range

The user must allow a minimum of 6 SClk cycles to elapse after

a reset (RESETN pin or CRa initiated) of the device terminates

before initiating a new bus cycle.

SC28L194 Datasheet(PDF) 36 Page - NXP Semiconductors

SC28L194 Datasheet(HTML) 36 Page - NXP Semiconductors

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