RT5752 datasheet(23/32 Pages) RICHTEK

23 / 32 page

RT5752

DS5752-03 November 2023

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Figure 7. Logic Control for the EN Pin

Figure 8. Resistive Divider for Under-Voltage Lockout

Threshold Setting

GND

VIN

REN

Enable

RT5752

GND

VIN

REN1

REN2

RT5752

Power-Good Output

The PG pin is an open-drain power-good indication output

and is to be connected to an external voltage source

through a pull-up resistor.

The external voltage source can be an external voltage

supply below 6V, VCC or the output of the RT5752 if the

output voltage is regulated under 6V. It is recommended

to connect a 100k

Ω between external voltage source to

PG pin.

Feedforward Capacitor (CFF)

The RT5752 is optimized for low duty-cycle applications,

and the control loop is stable with low ESR ceramic output

capacitors. This optimization makes circuit easily to

achieve stability with reasonable output capacitors, but it

also narrows the optimization of transient responses of

the converter. In higher duty-cycle applications (higher

output voltages or lower input voltage), the internal ripple

signal will increase in amplitude. Before the ACOT®control

loop can react to an output voltage fluctuation, the voltage

change on the feedback signal must exceed the internal

ripple amplitude. Because of the large internal ripple in

this condition, the response may become too slow and

may show an under-damped response. This can cause

some ringing in the output and is especially visible at

higher output voltage applications where duty-cycle is high.

The feedback network attenuation is large, adding to the

delay.As shown in Figure 9, adding a feedforward capacitor

(CFF) across the upper feedback resistor is recommended.

This increases the damping of the control system.

Figure 9. Feedback Loop with Feedforward Capacitor

GND

RFB1

RT5752

RFB2

CFF

COUT

VOUT

Loop stability can be checked by viewing the load transient

response. A load step with a speed that exceeds the

converter bandwidth must be applied. For ACOT®, loop

bandwidth can be in the order of 100 to 200kHz, so a load

step with 500ns maximum rise time (di/dt 2A/

μs) ensures

the excitation frequency is sufficient. It is important that

the converter operates in PWM mode, outside the light

load efficiency range, and below any current limit threshold.

A load transient from 30% to 60% of maximum load is

reasonable which is shown in Figure 10.



FB1

FB2











30% Load

60% Load

fCO

Figure 10. Example of Measuring the Converter fCO by

Fast Load Transient

CFF can be calculated base on below equation :

The loop bandwidth can be obviously extended by the

optimized feedforward capacitor, while the control system

is still maintaining an acceptable stability. However, the

inappropriate feedforward capacitor might cause the

insufficient gain margin or phase margin result in the

control system to be instability. Therefore, the feedforward

capacitor should be designed in a good compromise

between loop bandwidth improvement and acceptable

stability.

RT5752 Datasheet(PDF) 23 Page - Richtek Technology Corporation

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