LTM4682 datasheet(44/130 Pages) AD

44 / 130 page

LTM4682

Rev. 0

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OPERATION

applies primarily to the MFR_FAULT_LOG command. The

timeout period defaults to 32ms.

The user is encouraged to use as high a clock rate as

possible to maintain efficient data packet transfer between

all devices sharing the serial bus interface. The LTM4682

supports the full PMBus frequency range from 10kHz

to 400kHz.

SIMILARITY BETWEEN PMBus, SMBus AND I2C

2-WIRE INTERFACE

The PMBus 2-wire interface is an incremental extension of

the SMBus. The SMBus is built upon I2C with some minor

differences in timing, DC parameters, and protocol. The

PMBus/SMBus protocols are more robust than simple I2C

byte commands because PMBus/SMBus provide time-

outs to prevent persistent bus errors and optional packet

error checking (PEC) to ensure data integrity. In general,

a main device that can be configured for I2C communica-

tion can be used for PMBus communication with little or

no change to hardware or firmware. Repeat start (restart)

is not supported by all I2C controllers but is required for

SMBus/PMBus reads. If a general-purpose I2C controller

is used, check that repeat start is supported.

The LTM4682 supports the maximum SMBus clock

speed of 100kHz and is compatible with the higher speed

PMBus specification (between 100kHz and 400kHz) if

MFR_COMMON polling or clock stretching is enabled. For

robust communication and operation see the Note section

in the PMBus Command Summary section. Clock stretch-

ing is enabled by asserting bit 1 of MFR_CONFIG_ALL.

For a description of the minor extensions and exceptions

PMBus makes to SMBus, refer to PMBus Specification

Part 1 Revision 1.2: Paragraph 5: Transport. To describe

the differences between SMBus and I2C, refer to System

Management Bus (SMBus) Specification Version 2.0:

Appendix B—Differences Between SMBus and I2C.

PMBus SERIAL DIGITAL INTERFACE

The LTM4682 communicates with a host (main device)

using the standard PMBus serial bus interface. The

PMBus Timing Diagram, Figure 6, shows the timing rela-

tionship of the signals on the bus. The two-bus lines,

SDA and SCL, must be high when the bus is not in use.

External pull-up resistors or current sources are required

on these lines. The LTM4682 is a subordinate device. The

main device can communicate with the LTM4682 using

the following formats.

Main Transmitter, Subordinate Receiver

Main Receiver, Subordinate Transmitter

The following PMBus protocols are supported.

Write Byte, Write Word, Send Byte

Read Byte, Read Word, Block Read, Block Write

Alert Response Address

Figure 7 to Figure 24 illustrate the aforementioned PMBus

protocols. All transactions support PEC and GCP (group

command protocol). The Block Read supports 255 bytes

of returned data. For this reason, the PMBus timeout may

be extended when reading the fault log.

Figure 7 is the key to the protocol diagrams in this section.

PEC is optional. A value shown below a field in Figure 7 to

Figure 24 is a mandatory value for that field.

The data formats implemented by PMBus are:

Main transmitter transmits to an subordinate receiver.

The transfer direction, in this case, has not been

changed.

Main device reads the subordinate immediately after

the first byte. At the moment of the first acknowledge-

ment (provided by the subordinate receiver), the main

transmitter becomes a main receiver, and the subordi-

nate receiver becomes the subordinate transmitter.

Combined format. During a change of direction within

a transfer, the main device repeats both a start condi-

tion and the subordinate address but with the R/W bit

reversed. In this case, the main receiver terminates the

transfer by generating a NACK on the last byte of the

transfer and a STOP condition.

See Figure 7 for a legend.

Handshaking features are included to ensure robust sys-

tem communication. See the PMBus Communication and

Command Processing subsection of the Applications

Information section for further details.

LTM4682 Datasheet(PDF) 44 Page - Analog Devices

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