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MPM54313 Datasheet(PDF) 16 Page - Monolithic Power Systems

Part # MPM54313
Description  16V, Triple 3A Power Module with I2C Interface
PDF  49 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MPM54313 Datasheet(HTML) 16 Page - Monolithic Power Systems

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MPM54313
– 16V, TRIPLE 3A POWER MODULE WITH I2C
MPM54313 Rev. 1.0
MonolithicPower.com
16
5/7/2024
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2024 MPS. All Rights Reserved.
Over-Current Protection (OCP) and Short-
Circuit Protection (SCP)
The MPM54313 has fixed 3.6A valley current
limit control. When the low-side MOSFET (LS-
FET) is turning on, the inductor current (IL) is
monitored. If the sensed IL exceeds the valley
current limit threshold, the device sends an over-
current
(OC)
fault
warning
via
OC_STATUS_CLEAR
(2Ah).
The
high-side
MOSFET (HS-FET) is not allowed to turn on until
the valley current drops below the OC threshold.
Meanwhile, VOUT drops until it falls below its UV
threshold.
If the UV and OC conditions are both triggered,
OCP latches the device off. This means that the
chip disables the output power stage. The
MPM54313 does not automatically turn on again
until the UV and OCP conditions are removed,
and power is cycled on EN.
Output Discharge
To discharge the output capacitor
’s energy
during the power-off sequence or shutdown
sequence, there is discharge path from the VOx
pin to ground. The discharge function can be
enabled via the MTP interface, as well as the
discharge resistor.
Soft Start and Soft Stop
The MPM54313 employs a soft-start and soft-
stop mechanism to ensure smooth output during
the power-on and power-off sequences.
When the part is enabled and the BST voltage
reaches its rising threshold, the internal digital-
to-analog converter (DAC) outputs a ramp
voltage (reference voltage). VOUT smoothly
ramps up with the reference voltage. When the
DAC output reaches the final voltage, it stops at
that level. At this point, soft start finishes and the
device enters steady state operation.
When the part is disabled, the internal DAC
ramps down the reference voltage. The output
voltage follows the soft-stop slew rate with the
reference voltage until the output drops to 0.15V.
Then soft stop is finished, and the output is
discharged by a 30
Ω discharge resistor.
The start-up delay, shutdown delay, and soft-
start and soft-stop time can be configured via the
MTP.
Interleaving for Buck A and Buck B
The MPM54313 supports 2-phase interleaving
mode for buck A and buck B by setting
PROTECT_REG (14h), bit[5] = 1. VSA+ should
be connected to VSB+ for interleaving work
mode.
Figure 4 shows how the internal SET signal is
triggered when buck A/
B’s FB signal is below the
internal REF signal. When the SET signal
becomes high, only one phase’s pulse-width
modulation (PWM) output becomes high; the
next time SET becomes high, the next phase
’s
PWM output becomes high. This process
achieves automatic interleaving.
When buck A and buck B work in dual-phase
interleaving operation mode, the MPM54313
senses two phase currents and automatically
tunes the
buck’s on time (tON) to achieve active
paralleled current balancing.
VFB
VREF
SET
SWA
SWB
Figure 4: Dual-Phase Interleaving Mode
Active Voltage Positioning (AVP)
The
MPM54313
supports
active
voltage
positioning (AVP) by setting the AVP_EN bits
(ACTIVE_POSITION_ENABLE_A/B (71h), bit[7]
and
ACTIVE_POSITION_ENABLE_C
(79h),
bit[7]) to 1 via the I2C. Once enabled, the output
voltage of the corresponding channel drops in
proportion with the load current. VDROOP and VOUT
can be calculated with Equation (1) and Equation
(2), respectively:
VDROOP = IOUT x RDROOP
(1)
VOUT = VREF - VDROOP
(2)
Where VDROOP is the droop voltage, RDROOP is the
droop resistance with a typical value of 40m
Ω,
and VREF is the reference voltage of each
channel.
The AVP function enables on-demand parallel
operation, where the three outputs can be
paralleled in any combination without pre-setting
any registers (see Figure 5 on page 17). The
current of the paralleled channel(s) is inherently
balanced by the droop voltage created by the
AVP function.



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