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AM3359 Datasheet(PDF) 109 Page - Texas Instruments |
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AM3359 Datasheet(HTML) 109 Page - Texas Instruments |
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109 / 256 page ![]() AM335x XTALIN VSS_OSC XTALOUT LVCMOS Digital Clock Source VDDS_OSC Copyright © 2016, Texas Instruments Incorporated 109 AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351 www.ti.com SPRS717L – OCTOBER 2011 – REVISED MARCH 2020 Submit Documentation Feedback Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Power and Clocking Copyright © 2011–2020, Texas Instruments Incorporated (1) Initial accuracy, temperature drift, and aging effects should be combined when evaluating a reference clock for this requirement. 6.2.2.2 OSC0 LVCMOS Digital Clock Source Figure 6-11 shows the recommended oscillator connections when OSC0 is connected to an LVCMOS square-wave digital clock source. The LVCMOS clock source is connected to the XTALIN terminal. The ground for the LVCMOS clock source and VSS_OSC should be connected directly to the nearest PCB digital ground (VSS). In this mode of operation, the XTALOUT terminal should not be used to source any external components. The PCB design should provide a mechanism to disconnect the XTALOUT terminal from any external components or signal traces that may couple noise into OSC0 via the XTALOUT terminal. The XTALIN terminal has a 15- to 40-kΩ internal pulldown resistor which is enabled when OSC0 is disabled. This internal resistor prevents the XTALIN terminal from floating to an invalid logic level which may increase leakage current through the oscillator input buffer. Figure 6-11. OSC0 LVCMOS Circuit Schematic Table 6-4. OSC0 LVCMOS Reference Clock Requirements NAME DESCRIPTION MIN TYP MAX UNIT ƒ(XTALIN) Frequency, LVCMOS reference clock 19.2, 24, 25, or 26 MHz Frequency, LVCMOS reference clock stability and tolerance(1) –50 50 ppm tdc(XTALIN) Duty cycle, LVCMOS reference clock period 45% 55% tjpp(XTALIN) Jitter peak-to-peak, LVCMOS reference clock period –1% 1% tR(XTALIN) Time, LVCMOS reference clock rise 5 ns tF(XTALIN) Time, LVCMOS reference clock fall 5 ns 6.2.2.3 OSC1 Internal Oscillator Clock Source Figure 6-12 shows the recommended crystal circuit for OSC1 of the ZCE package and Figure 6-13 shows the recommended crystal circuit for OSC1 of the ZCZ package. TI recommends that preproduction PCB designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator operation when combined with production crystal circuit components. In most cases, Rbias is not required and Rd is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator performance with production crystal circuit components installed on preproduction PCBs. The RTC_XTALIN terminal has a 10- to 40-kΩ internal pullup resistor which is enabled when OSC1 is disabled. This internal resistor prevents the RTC_XTALIN terminal from floating to an invalid logic level which may increase leakage current through the oscillator input buffer. |
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