AM3359 datasheet(115/256 Pages) TI1

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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351

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SPRS717L – OCTOBER 2011 – REVISED MARCH 2020

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Peripheral Information and Timings

The AM335x device contains many peripheral interfaces. In order to reduce package size and lower

overall system cost while maintaining maximum functionality, many of the AM335x terminals can multiplex

up to eight signal functions. Although there are many combinations of pin multiplexing that are possible,

only a certain number of sets, called I/O Sets, are valid due to timing limitations. These valid I/O Sets were

carefully chosen to provide many possible application scenarios for the user.

Texas Instruments has developed a Windows-based application called Pin Mux Utility that helps a system

designer select the appropriate pin-multiplexing configuration for their AM335x-based product design. The

Pin Mux Utility provides a way to select valid I/O Sets of specific peripheral interfaces to ensure the pin-

multiplexing configuration selected for a design only uses valid I/O Sets supported by the AM335x device.

7.1

Parameter Information

The data provided in the following Timing Requirements and Switching Characteristics tables assumes the

device is operating within the Recommended Operating Conditions defined in Section 5, unless otherwise

noted.

7.1.1

Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data manual do not include delays by board routings. As a

good board design practice, such delays must always be taken into account. Timing values may be

adjusted by increasing or decreasing such delays. TI recommends using the available I/O buffer

information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external

logic hardware such as buffers may be used to compensate any timing differences.

The timing parameter values specified in this data manual assume the SLEWCTRL bit in each pad control

For the mDDR(LPDDR), DDR2, DDR3, DDR3L memory interface, it is not necessary to use the IBIS

models to analyze timing characteristics. TI provides a PCB routing rules solution that describes the

routing rules to ensure the mDDR(LPDDR), DDR2, DDR3, DDR3L memory interface timings are met.

7.2

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic

manner.

7.3

OPP50 Support

Some peripherals and features have limited support when the device is operating in OPP50. A complete

list of these limitations follows.

Not supported when operating in OPP50:

Reduced performance when operating in

OPP50:

•

CPSW

•

DDR3

•

DEBUGSS-Trace

•

GPMC Asynchronous Mode

•

LCDC LIDD Mode

•

MDIO

•

PRU-ICSS MII

•

DDR2

•

DEBUGSS-JTAG

•

GPMC Synchronous Mode

•

LCDC Raster Mode

•

LPDDR

•

McASP

•

McSPI

•

MMCSD

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