AM3359 datasheet(145/256 Pages) TI1

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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351

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SPRS717L – OCTOBER 2011 – REVISED MARCH 2020

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Peripheral Information and Timings

Table 7-32. GPMC and NAND Flash Switching Characteristics—Asynchronous Mode

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

GNF0

tw(wenV)

Pulse duration, output write enable gpmc_wen

valid

A(1)

GNF1

td(csnV-wenV)

Delay time, output chip select gpmc_csn[x](13)

valid to output write enable gpmc_wen valid

B(2) – 0.2

B(2) + 2.0

B(2) – 5

B(2) + 5

GNF2

tw(cleH-wenV)

Delay time, output lower-byte enable and

command latch enable gpmc_be0n_cle high to

output write enable gpmc_wen valid

C(3) – 0.2

C(3) + 2.0

C(3) – 5

C(3) + 5

GNF3

tw(wenV-dV)

Delay time, output data gpmc_ad[15:0] valid to

output write enable gpmc_wen valid

D(4) – 0.2

D(4) + 2.0

D(4) – 5

D(4) + 5

GNF4

tw(wenIV-dIV)

Delay time, output write enable gpmc_wen

invalid to output data gpmc_ad[15:0] invalid

E(5) – 0.2

E(5) + 5

E(5) – 5

E(5) + 5

GNF5

tw(wenIV-cleIV)

Delay time, output write enable gpmc_wen

invalid to output lower-byte enable and command

latch enable gpmc_be0n_cle invalid

F(6) – 0.2

F(6) + 2.0

F(6) – 5

F(6) + 5

GNF6

tw(wenIV-csnIV)

Delay time, output write enable gpmc_wen

invalid to output chip select gpmc_csn[x](13)

invalid

G(7) – 0.2

G(7) + 2.0

G(7) – 5

G(7) + 5

GNF7

tw(aleH-wenV)

Delay time, output address valid and address

latch enable gpmc_advn_ale high to output write

enable gpmc_wen valid

C(3) – 0.2

C(3) + 2.0

C(3) – 5

C(3) + 5

GNF8

tw(wenIV-aleIV)

Delay time, output write enable gpmc_wen

invalid to output address valid and address latch

enable gpmc_advn_ale invalid

F(6) – 0.2

F(6) + 2.0

F(6) – 5

F(6) + 5

GNF9

tc(wen)

Cycle time, write

H(8)

GNF10

td(csnV-oenV)

Delay time, output chip select gpmc_csn[x](13)

valid to output enable gpmc_oen valid

I(9) – 0.2

I(9) + 2.0

I(9) – 5

I(9) + 5

GNF13

tw(oenV)

Pulse duration, output enable gpmc_oen valid

K(10)

GNF14

tc(oen)

Cycle time, read

L(11)

GNF15

tw(oenIV-csnIV)

Delay time, output enable gpmc_oen invalid to

output chip select gpmc_csn[x](13) invalid

M(12) – 0.2

M(12) + 2.0

M(12) – 5

M(12) + 5

(1) A = (WEOffTime – WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

(2) B = ((WEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK(14)

(3) C = ((WEOnTime – ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – ADVExtraDelay)) × GPMC_FCLK(14)

(4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK(14)

(5) E = ((WrCycleTime – WEOffTime) × (TimeParaGranularity + 1) – 0.5 × WEExtraDelay) × GPMC_FCLK(14)

(6) F = ((ADVWrOffTime – WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – WEExtraDelay)) × GPMC_FCLK(14)

(7) G = ((CSWrOffTime – WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – WEExtraDelay)) × GPMC_FCLK(14)

(8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)

(9) I = ((OEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay)) × GPMC_FCLK(14)

(10) K = (OEOffTime – OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK(14)

(11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14)

(12) M = ((CSRdOffTime – OEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – OEExtraDelay)) × GPMC_FCLK(14)

(13) In gpmc_csn[x], x is equal to 0, 1, 2, 3, 4, or 5.

(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

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