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H838024 Datasheet(PDF) 44 Page - Renesas Technology Corp |
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H838024 Datasheet(HTML) 44 Page - Renesas Technology Corp |
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44 / 697 page ![]() Section 1 Overview Rev. 7.00 Mar 10, 2005 page 2 of 652 REJ09B0042-0700 Table 1.1 Features Item Specification CPU High-speed H8/300L CPU • General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) • Operating speed Max. operating speed: 8 MHz (5 MHz for HD64F38024 and H8/38024S Group) Add/subtract: 0.25 µs (operating at 8 MHz), 0.4 µs (operating at φ = 5 MHz) Multiply/divide: 1.75 µs (operating at 8 MHz), 2.8 µs (operating at φ = 5 MHz) Can run on 32.768 kHz or 38.4 kHz subclock (32.768 kHz only for H8/38124 Group) • Instruction set compatible with H8/300 CPU Instruction length of 2 bytes or 4 bytes Basic arithmetic operations between registers MOV instruction for data transfer between memory and registers • Typical instructions Multiply (8 bits × 8 bits) Divide (16 bits ÷ 8 bits) Bit accumulator Register-indirect designation of bit position Interrupts 22 interrupt sources • 13 external interrupt sources (IRQ 4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0, IRQAEC) • 9 internal interrupt sources |
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