OPA830 datasheet(32/56 Pages) TI

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elements in half and add a low-impedance path, such as a capacitor or a DC reference, between the two RG

values.

Vindiff

OPA838

R1 500 Ÿ

R2 500 Ÿ

VCM

RF 3.57 NŸ

RG1 88.7 Ÿ

CCM

10nF

VCC

Vodiff

High Gain

Differential

I/O

VEE

Figure 8-4. High-Gain Differential I/O Stage

Integrated results are available, but the OPA838 provides a low-power, high-frequency result. For best CMRR

performance, match the resistors. A good rule is CMRR is approximately equal to the resistor tolerance;

therefore, a 0.1% tolerance provides approximately 60-dB CMRR.

8.2.1.1 Design Requirements

As an example design, start with the circuit in Figure 8-4.

• Set the target gain and split the RG element in half. For this example, target a gain of 41 V/V.

• Assess the DC common-mode biasing on the noninverting inputs. The DC biasing must be in range and have

a gain of 1 to the output. This is not illustrated in Figure 8-3.

• If a DC reference is used as the mid-R G bias, setting the reference equal to the noninverting input

bias voltage sets the output common-mode to that voltage. Using a capacitor as illustrated in Figure 8-3

accomplishes the same results.

OPA838

SBOS867D – AUGUST 2017 – REVISED SEPTEMBER 2024

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OPA830 Datasheet(PDF) 32 Page - Texas Instruments