OPA830 datasheet(33/56 Pages) TI

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8.2.1.2 Detailed Design Procedure

• Set the total R G value near the high gain values using Table 8-1. This 178-Ω total must be split for a center

tap to increase the common-mode noise gain, as shown by the 88.7-Ω value in Figure 8-4.

• Set RF using a standard value near the calculated from solving Equation 1 using half of the total RG value.

• Simulate the common-mode noise with different elements on the RG center tap as shown in Figure 8-5.

Decide which is most appropriate to the application.

The common-mode loop instability without the RG center tap is not often apparent in the closed-loop differential

simulations. The common-mode loop instability without the RG center tap can often be detected in a common-

mode output-noise simulation as Figure 8-5 shows. Grounding the inputs Figure 8-4 and running an output-noise

simulation for the common-mode tap point in Figure 8-3 shows a peaking in the noise at high frequency. This

peaking indicates low-phase margin for the common-mode loop. Figure 8-5 shows this peaking in the lowest

noise curve, with two options for improving phase margin. The first option used in Figure 8-4 is a capacitor to

ground set to increase the common-mode noise gain only at higher frequencies. This increase can be seen by

the peaking in the common-mode noise of Figure 8-5. Another alternative is to provide a dc voltage reference

on the RG center tap. This method raises the common-mode noise gain from dc and beyond. Neither of these

latter two options show any evidence of low phase-margin peaking. These two options do increase the output

common-mode noise significantly at lower frequencies. Typically, an increase in output common-mode noise is

more acceptable than low-phase margin because the next stage (FDA, ADC, differential to single stage) rejects

common-mode noise.

Using the 10-nF center tap capacitor, Figure 8-6 shows the differential I/O small-signal response showing the

expected 300 MHz / 41 ≈ 7.3 MHz closed-loop bandwidth. The capacitor to ground between the RG elements

does not impact the differential frequency response.

8.2.1.3 Application Curves

Frequency (Hz)

100

120

140

160

180

10k

100k

10M

100M

Diff

No center tap

10 nF

Ground

Figure 8-5. Common-Mode Output Noise for

Differential I/O Design

Frequency (MHz)

100

D074

Figure 8-6. Differential Small-Signal Frequency

Response

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OPA838

SBOS867D – AUGUST 2017 – REVISED SEPTEMBER 2024

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