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OPA830 Datasheet(PDF) 37 Page - Texas Instruments

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Part # OPA830
Description  OPA838 1mA, 300MHz Gain Bandwidth, Voltage-Feedback Op Amp
PDF  56 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

OPA830 Datasheet(HTML) 37 Page - Texas Instruments

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8.4 Layout
8.4.1 Layout Guidelines
The OPA838 EVM can be used as a reference when designing the circuit board. TI recommends following the
EVM layout of the external components near to the amplifier, ground plane construction, and power routing as
closely as possible. General guidelines are listed below:
1. Signal routing must be direct and as short as possible into and out of the op amp.
2. The feedback path must be short and direct avoiding vias if possible.
3. Ground or power planes must be removed from directly under the negative input and output pins of the
amplifier.
4. TI recommends placing a series output resistor as close to the output pin as possible when driving capacitive
or matched loads.
5. A 2.2-µF power-supply decoupling capacitor must be placed within two inches of the device and can be
shared with other op amps. For split-supply operation, a capacitor is required for both supplies.
6. A 0.1-µF power-supply decoupling capacitor must be placed as close to the supply pins as possible,
preferably within 0.1 inch. For split-supply operation, a capacitor is required for both supplies.
7. The PD pin uses logic levels referenced off the negative supply. If the pin is not used, the pin must tie to the
positive supply to enable the amplifier. If the pin is used, the pin must be actively driven. A bypass capacitor
is not necessary, but is used for EMI rejection in noisy environments.
8.4.2 Layout Example
Place bypass capacitors
close to power pins
Place input resistor close to pin 4
to minimize stray capacitance
Place output resistors close
to output pins to minimize
parasitic capacitance
Ground and power plane removed
from inner layers
Ground and power plane exist on
inner layers
1
2
6
4
5
Place bypass capacitors
close to power pins
Remove GND and Power plane
under pins 1 and 4 to minimize
stray PCB capacitance
Place feedback resistor on the bottom
of PCB between pins 4 and 6
Power control (disable) pin
Must be driven
Non-inverting input
terminated in 50 Ÿ
3
Figure 8-9. EVM Layout Example
www.ti.com
OPA838
SBOS867D – AUGUST 2017 – REVISED SEPTEMBER 2024
Copyright © 2024 Texas Instruments Incorporated
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37
Product Folder Links: OPA838



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