OPA830 datasheet(6/56 Pages) TI

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6.5 Electrical Characteristics VS = 5 V (continued)

at VS+ = 5 V, VS– = 0 V, RF = 1 kΩ, RG = 200 Ω, RL = 2 kΩ, G = 6 V/V, input and output referenced to midsupply, and

TA ≈ 25°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TEST

LEVEL(1)

INPUT

Common-mode input range, low

TA ≈ 25°C, CMRR > 92 dB

VS– – 0.2

VS– – 0

TA = –40°C to +125°C, CMRR > 92 dB

VS– – 0

Common-mode input range, high

TA ≈ 25°C, CMRR > 92 dB

VS+ – 1.3

VS+ – 1.2

TA = –40°C to +125°C, CMRR > 92 dB

VS+ – 1.3

CMRR

Common-mode rejection ratio

105

Input impedance common-mode

35 || 1

MΩ || pF

Input impedance differential mode

30 || 1.3

kΩ || pF

OUTPUT

VOL

Output voltage, low

TA ≈ 25°C, G = 6

VS– + 0.05

VS– + 0.1

TA = –40°C to +125°C, G = 6

VS– + 0.05

VS– + 0.1

VOH

Output voltage, high

TA ≈ 25°C, G = 6

VS+ – 0.1 VS+ – 0.05

TA = –40°C to +125°C, G = 6

VS+ – 0.2

VS+ – 0.1

Maximum current into a resistive

load

TA ≈ 25°C, ±1.53 V into 41.3 Ω, VIO < 2 mV

±35

±40

Linear current into a resistive load

TA ≈ 25°C, ±1.81 V into 70.6 Ω, AOL > 80 dB

±25

±28

TA = –40°C to +125°C, ±1.58 V into 70.6 Ω,

AOL > 80 dB

±22

±25

DC output impedance

G = 6

0.02

POWER SUPPLY

Specified operating voltage

2.7

5.4

Quiescent operating current

TA ≈ 25°C (DXB package)(6)

900

960

1025

µA

TA ≈ 25°C (6)

913

960

1025

TA = –40°C to +125°C

700

960

1365

dIq/dT

Quiescent current temperature

coefficient

TA = –40°C to +125°C

2.6

3.4

µA/°C

+PSRR

Positive power-supply rejection

ratio

110

–PSRR

Negative power-supply rejection

ratio

105

POWER DOWN (Pin Must be Driven, SOT23-6 and SC70-6)

Enable voltage threshold

Specified on above VS–+ 1.5 V

1.5

Disable voltage threshold

Specified off below VS–+ 0.55 V

0.55

Disable pin bias current

PD = VS– to VS+

–50

Power-down quiescent current

PD = 0.55 V

0.1

µA

Turn-on time delay

Time from PD = high to VOUT = 90% of final

value

1.7

µs

Turn-off time delay

Time from PD = low to VOUT = 10% of original

value

100

(1)

Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and

simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.

(2)

This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (0.8 × VPEAK / √2) × 2π × f–3dB

where this f–3dB is the typical measured 4-VPP bandwidth at gains of 6 V/V.

(3)

Current is considered positive out of the pin.

(4)

Input offset voltage drift, input bias current drift, and input offset current drift typical specifications are mean ± 1σ characterized by the

full temperature range end-point data. Maximum drift specifications are set by the min, max packaged test range on the wafer-level

screened drift. Drift is not specified by the final automated test equipment (ATE) or by QA sample testing.

(5)

Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end

points, computing the difference, and dividing by the temperature range.

(6)

The typical specification is at 25°C TJ. The minimum and maximum limits are expanded for the ATE to account for an ambient range

from 22°C to 32°C with a 4-µA/°C temperature coefficient on the supply current.

OPA838

SBOS867D – AUGUST 2017 – REVISED SEPTEMBER 2024

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