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PM4388 Datasheet(PDF) 60 Page - PMC-Sierra, Inc |
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PM4388 Datasheet(HTML) 60 Page - PMC-Sierra, Inc |
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60 / 284 page ![]() PM4388 TOCTL DATA SHEET PMC-960840 ISSUE 5 OCTAL T1 FRAMER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 44 DS1 stream. The IBCD must still be programmed to detect the desired pattern, and otherwise operates unchanged. Reserved Reserved for future use. AUTOYELLOW: When the AUTOYELLOW bit is set to logic 1, then whenever ALMI declares a Red alarm in the ingress direction, XBAS will transmit a Yellow alarm in the egress direction. When AUTOYELLOW is set to logic 0, XBAS will only transmit a Yellow alarm when the XYEL bit is set in the XBAS Alarm Transmit Register (reg. 045H, 0C5H, 145H, 1C5H, 245H, 2C5H, 345H, 3C5H). Note that the Red alarm from ALMI is not deasserted on detection of AIS. AUTORED: The AUTORED bit allows global trunk conditioning to be applied to the ingress data stream, ID[x], immediately upon declaration of Red carrier failure alarm. When AUTORED is set to logic 1, the data on ID[x] for each channel is replaced with the data contained in the data trunk conditioning registers within RPSC while Red CFA is declared. When AUTORED is set to logic 0, the ingress data is not automatically conditioned when Red CFA is declared. AUTOOOF: The AUTOOOF bit allows global trunk conditioning to be applied to the ingress data stream, ID[x], immediately upon declaration of out of frame (OOF). When AUTOOOF is set to logic 1, then while OOF is declared, the data on ID[x] for each channel is replaced with the data contained in the data trunk conditioning registers within RPSC. When AUTOOOF is set to logic 0, the ingress data is not automatically conditioned by RPSC when OOF is declared. However, if the ELST is not bypassed, then the ELST trouble code will still be inserted in channel data while OOF is declared. RPSC data and signaling trunk conditioning overwrites the ELST trouble code. AUTOUPDATE When AUTOUPDATE is logic 1, the PMON and PRGD registers in the appropriate framer are automatically updated once every 8000 receive frame periods, i.e. once a second, timed to the receive line. If the INTE bit is set in the PMON Interrupt/Enable register, then the PMON will interrupt the microprocessor as soon as the results are available in the PMON registers. The results will then be available for reading for the next second, until they are overwritten by the next update. The OVR bit in the PMON Interrupt/Enable register indicates such an overwrite by going to logic 1. |
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