PM4388 datasheet(79/284 Pages) PMC

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PM4388 TOCTL

DATA SHEET

PMC-960840

ISSUE 5

OCTAL T1 FRAMER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Mode Description

Bit Settings

Transmit Line Clock

Options

Clock Master: Full DS1

or NxDS0.

Egress data is clocked

by TLCLK[x], and TJAT

FIFO is automatically

bypassed.

In NxDS0 mode, a

gapped version of

TLCLK[x] is provided on

ECLK[x], which only

clocks during the desired

channels.

The TJAT PLL is used to

generate TLCLK[x] from

a reference clock.

EMODE[1:0] = 0X

HSBPSEL

FIFOBYP

OCLKSEL

CTCLKSEL =0

SMCLKO

CECLK2M

The setting

PLLREF[1:0]=00 is

reserved and should not

be used.

When PLLREF[1:0]=01,

TLCLK[x] is a jitter-

attenuated clock

referenced to CECLK.

When PLLREF[1:0]=10,

TLCLK[x] is a jitter-

attenuated clock

referenced to RLCLK[x]

When PLLREF[1:0]=11,

TLCLK[x] is a jitter-

attenuated clock

referenced to CTCLK

Clock Master: Full DS1

or NxDS0

Egress data is clocked

by TLCLK[x], and TJAT

FIFO is automatically

bypassed.

In NxDS0 mode, a

gapped version of

TLCLK[x] is provided on

ECLK[x], which only

clocks during the desired

channels.

The TJAT PLL is

unused.

EMODE[1:0] = 0X

HSBPSEL

FIFOBYP

CECLK2M

PLLREF[1:0] =XX

When OCLKSEL = 1,

TLCLK[x] = CTCLK.

When OCLKSEL = 0,

SMCLKO = 1, and

CTCLKSEL =0, then

TLCLK[x] = CTCLK÷8.

When OCLKSEL = 0,

SMCLKO = 1, and

CTCLKSEL =1, then

TLCLK[x] = XCLK÷24.

Notes:

1. When the internally gapped clock is used as the TJAT PLL reference, the

TJAT divisors N1 and N2 should both be set to C0H.

PM4388 Datasheet(PDF) 79 Page - PMC-Sierra, Inc

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