PM4388 datasheet(61/284 Pages) PMC

61 / 284 page

PM4388 TOCTL

DATA SHEET

PMC-960840

ISSUE 5

OCTAL T1 FRAMER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

When AUTOUPDATE is logic 1, the microprocessor can still initiate additional

updates by writing to any of the PMON counter registers or to the

Revision/Chip ID/Global PMON Update register (register 00CH), but care

should be taken not to initiate a second update in a given PMON before the

first is completed, which can lead to unpredictable results.

Similarly, the XFERE bit in the PRGD Interrupt Enable/Status Register may

be set, allowing the PRGD to interrupt the microprocessor when a PRGD

update has been completed. PRGD and PMON perform updates in the same

number of clock cycles, so only one of the two interrupts need be enabled.

The OVR bit in the same register indicates that data has been overwritten

without being read. As is the case for the PMON, additional updates of the

PRGD may be initiated by the microprocessor via the Revision/Chip ID/Global

PMON Update register, and care must be taken to avoid initiating an update

while another update is in progress.

PM4388 Datasheet(PDF) 61 Page - PMC-Sierra, Inc