PM4388 datasheet(97/284 Pages) PMC

97 / 284 page

PM4388 TOCTL

DATA SHEET

PMC-960840

ISSUE 5

OCTAL T1 FRAMER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

SYNC:

The SYNC bit enables the PLL to synchronize the phase delay between the

FIFO input and output data to the phase delay between reference clock input

and smooth output clock at the PLL. For example, if the PLL is operating so

that the smooth output clock lags the reference clock by 24 UI, then the

synchronization pulses that the PLL sends to the FIFO will force its output

data to lag its input data by 24 UI. When SYNC is set to logic 1, then the

RJAT divisors (N1 and N2) must be set so that N1+1 is a multiple of 48

decimal, and N2+1 is a multiple of 48 decimal.

LIMIT:

The LIMIT bit enables the PLL to limit the jitter attenuation by enabling the

FIFO to increase or decrease the frequency of the smooth output clock

whenever the FIFO is within one unit interval (UI) of overflowing or

underflowing. This limiting of jitter ensures that no data is lost during high

phase shift conditions. When LIMIT is set to logic 1, the PLL jitter attenuation

is limited. When LIMIT is set to logic 0, the PLL is allowed to operate normally.

PM4388 Datasheet(PDF) 97 Page - PMC-Sierra, Inc