PM4388 datasheet(13/284 Pages) PMC

13 / 284 page

PM4388 TOCTL

DATA SHEET

PMC-960840

ISSUE 5

OCTAL T1 FRAMER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

xii

FIGURE 21- INGRESS INTERFACE: 2.048 MHZ CLOCK SLAVE MODE...... 204

FIGURE 22- EGRESS INTERFACE: 2.048 MHZ CLOCK SLAVE: EFP ENABLED

MODE................................................................................................... 205

FIGURE 23- EGRESS INTERFACE: 2.048 MHZ CLOCK SLAVE: EXTERNAL

SIGNALING MODE .............................................................................. 206

FIGURE 24- TYPICAL DATA FRAME.............................................................. 216

FIGURE 25- EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE ......... 217

FIGURE 26- PRGD PATTERN GENERATOR ................................................. 220

FIGURE 27- LINE LOOPBACK....................................................................... 224

FIGURE 28- DIAGNOSTIC DIGITAL LOOPBACK .......................................... 225

FIGURE 29- PER-DS0 LOOPBACK ............................................................... 226

FIGURE 30- BEE COUNT EXPECTED VS BIT ERROR RATE FOR ESF...... 231

FIGURE 31- BOUNDARY SCAN ARCHITECTURE........................................ 232

FIGURE 32- TAP CONTROLLER FINITE STATE MACHINE .......................... 234

FIGURE 33- INPUT OBSERVATION CELL (IN_CELL) ................................... 240

FIGURE 34- OUTPUT CELL (OUT_CELL)..................................................... 241

FIGURE 35- BIDIRECTIONAL CELL (IO_CELL)............................................ 241

FIGURE 36- LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS 242

FIGURE 37- MICROPROCESSOR READ ACCESS TIMING ......................... 247

FIGURE 38- MICROPROCESSOR WRITE ACCESS TIMING ....................... 249

FIGURE 39- XCLK=37.056 MHZ INPUT TIMING ........................................... 251

FIGURE 40- EGRESS INTERFACE TIMING - CLOCK SLAVE: EFP ENABLED

MODE................................................................................................... 252

FIGURE 41- EGRESS INTERFACE TIMING - CLOCK SLAVE: EXTERNAL

SIGNALING MODE .............................................................................. 253

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