PM7344 datasheet(247/293 Pages) PMC

247 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

231

a) If there is still data to send, then write the next data byte to the XFDL

Transmit Data Register;

b) If all bytes in the frame have been sent, then set the EOM bit in the XFDL

Configuration Register to logic 1.

4. If EOM bit was set to logic 1 in step 3b, then:

a) Read the XFDL Interrupt Status Register and check the UDR bit.

b) If UDR=1 then reset the UDR bit in the XFDL Interrupt Status Register

and the EOM bit in the XFDL Configuration Register to logic 0, and retransmit

the last frame.

5. Go to step 1.

Interrupt Mode

In the case of interrupt driven data transfer, the TDLINT[x] output is connected to

the interrupt input of the processor, and the interrupt service routine should

process the data exactly as described above for the polled mode. The INTE bit

in the XFDL Configuration Register must be set to logic 1. Alternately, the INTB

output can be connected to the interrupt input of the processor if the TDLINTE bit

of the Datalink Options Register is set to logic 1. If this mode is used, additional

polling of the Source Selection/Interrupt ID, Interrupt Source #1 and Interrupt

Source #2 registers must be performed to identify the cause of the interrupt

before initiating the interrupt service routine.

DMA-Controlled Mode

The XFDL can also be used with a DMA controller to process the frame data. In

this case, the TDLUDR[x] output is connected to the processor interrupt input.

The TDLINT[x] output of the XFDL is connected to the DMA request input of the

DMA controller. The INTE bit in the XFDL Configuration Register must be set to

logic 1 before enabling the XFDL. The DMA controller writes a data byte to the

XFDL whenever the TDLINT[x] output is high. If there is a problem during

transmission and an underrun condition occurs, then the TDLUDR[x] output goes

high and the processor is interrupted. The processor can then halt the DMA

controller, reset the UDR bit in the XFDL Interrupt Status Register, reset the

frame data pointers, and restart the DMA controller to resend the data frame.

After the message transmission is completed, the DMA controller must initiate a

write to set the EOM bit in the XFDL Configuration Register and then verify that

TDLUDR[x] is not set prior to setting EOM.

PM7344 Datasheet(PDF) 247 Page - PMC-Sierra, Inc