PM7344 datasheet(112/293 Pages) PMC

112 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

DCR:

The disable clock recovery (DCR) bit is used when RDP/RDD[x] and

RDN/RLCV[x] contain NRZ formatted data. When DCR is a logic 1, the

RCLKI[x] input contains the recovered clock. When DCR is a logic 0, the

clock is recovered from the RDP[x] and RDN[x] inputs.

SYNC:

The SYNC bit enables synchronization of the recovered clock (RCLKI[x]) to

the 8x clock when clock recovery is disabled. When SYNC is a logic 1,

RCLKI[x] transitions are synchronized to the rising edges of the 8x clock.

This bit must be set to logic 1 when clock recovery is disabled in T1 mode

(DCR is a logic 1, MODE[1:0] in Receive Configuration register is 00B). This

bit must be set to logic 0 if in E1 mode (MODE[1:0] in Receive Configuration

ALGSEL:

The Algorithm Select (ALGSEL) bit specifies the algorithm used by the DPLL

for clock and data recovery. The choice of algorithm determines the high

frequency input jitter tolerance of the CDRC. When ALGSEL is set to logic 1,

the CDRC jitter tolerance is increased to approach 0.5UIpp for jitter

frequencies above 20KHz. When ALGSEL is set to logic 0, the jitter

tolerance is increased for frequencies below 20KHz (i.e. the tolerance is

improved by 20% over that of ALGSEL=1 at these frequencies), but the

tolerance approaches 0.4UIpp at the higher frequencies.

O162:

When the E1 format is selected and the AMI bit is logic 0, the

Recommendation O.162 compatibility select bit (O162) allows selection

between two line code definitions:

1.) If O162 is a logic 0, a line code violation is indicated if the serial stream

does not match the verbatim HDB3 definition given in Recommendation

G.703. A bipolar violation that is not part of an HDB3 signature or a bipolar

violation in an HDB3 signature that is the same polarity as the last bipolar

violation results in a line code violation indication.

2.) If O162 is a logic 1, a line code violation is indicated by a LCV output

pulse if a bipolar violation is of the same polarity as the last bipolar violation,

as per Recommendation O.162.

PM7344 Datasheet(PDF) 112 Page - PMC-Sierra, Inc