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PM7344 Datasheet(PDF) 114 Page - PMC-Sierra, Inc |
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PM7344 Datasheet(HTML) 114 Page - PMC-Sierra, Inc |
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114 / 293 page ![]() PM7344 S/UNI-MPH DATA SHEET PMC-950449 ISSUE 6 MULTI-PHY USER NETWORK INTERFACE PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 98 Registers 012H, 112H, 212H and 312H: CDRC Interrupt Status Bit Type Function Default Bit 7 R LCVI 0 Bit 6 R LOSI 0 Bit 5 R LCSDI 0 Bit 4 R EXZI 0 Bit 3 Unused X Bit 2 Unused X Bit 1 Unused X Bit 0 R LOS 0 The bit positions LCVI, LOSI, LCSDI and EXZI of this register indicate which of the status events generated an interrupt. A logic 1 in these bit positions indicate that the corresponding event was detected; a logic 0 in these bit positions indicate that no corresponding event has been detected. The bit positions LCVI, LCSDI and EXZI are set on the assertion of a line code violation, a line code signature detection, and excessive zeros detection, respectively. LOSI is set on a change of state of the LOS alarm. Bits LCVI, LOSI, LCSDI and EXZI are cleared by reading this register. The current state of the LOS alarm can be determined by reading bit 0 of this register. |
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