PM7344 datasheet(147/293 Pages) PMC

147 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

131

Registers 034H, 134H, 234H and 334H: XFDL Configuration

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

Unused

Bit 4

R/W

EOM

Bit 3

R/W

INTE

Bit 2

R/W

ABT

Bit 1

R/W

CRC

Bit 0

R/W

EN:

The enable bit (EN) controls the overall operation of the XFDL. When the EN

bit is set to a logic 1, the XDFL is enabled and flag sequences are sent until

data is written into the XFDL Transmit Data register. When the EN bit is set

to logic 0, the XFDL is disabled.

CRC:

The CRC enable bit controls the generation of the CRC-CCITT frame check

sequence (FCS). Setting the CRC bit to logic 1 enables the CRC-CCITT

generator and the appends the 16 bit FCS to the end of each message.

When the CRC bit is set to logic 0, the FCS is not appended to the end of the

message. The CRC type used is the CRC-CCITT with generator polynomial

= x16 + x12 + x5 + 1. The high order bit of the FCS word is transmitted first.

ABT:

The Abort (ABT) bit controls the sending of the 7 consecutive ones HDLC

abort code. Setting the ABT bit to a logic 1 causes the 11111110 code to be

transmitted after the last byte from the XFDLTransmit Data Register is

transmitted. Aborts are continuously sent until this bit is reset to a logic 0.

INTE:

The INTE bit enables the generation of an interrupt via the TDLINT[x] output.

Setting the INTE bit to logic 1 enables the generation of an interrupt; setting

INTE to logic 0 disables the generation of an interrupt. If the TDLINTE bit is

also set to logic 1 in the Datalink Options register, the interrupt generated on

the TDLINT[x] output is also generated on the microprocessor INTB pin.

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