PM7344 datasheet(155/293 Pages) PMC

155 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

139

2) An abort sequence is detected while not in the receiving all-ones state

and the byte, written to the FIFO due to the detection of the abort sequence,

is being read from the FIFO,

3) The first flag has been detected and the dummy byte, written into the

FIFO when the RFDL changes from the receiving all-ones state to the

receiving flags state, is being read from the FIFO,

4) Immediately on detection of FIFO overrun.

The EOM bit is passed through the FIFO with the Data so that the Status will

correspond to the Data just read from the FIFO.

FLG:

The flag bit (FLG) is set if the RFDL has detected the presence of the HDLC

flag sequence (01111110) in the data. FLG is reset only when the HDLC

abort sequence (01111111) is detected in the data or when the RFDL is

disabled. This bit is passed through the FIFO with the Data so that the Status

will correspond to the Data just read from the FIFO. The reception of bit-

oriented codes over the data link will also force an abort due to its eight ones

pattern.

OVR:

The Receiver Overrun bit (OVR) is set when data is written over unread data

in the FIFO. This bit is not reset until after the Status register is read. While

OVR is high, the RFDL and FIFO are held in the reset state, causing the FLG

and EOM bits in the status register to be reset also.

FE:

The FIFO Empty bit (FE) is high when the last FIFO entry is read and goes

low when the FIFO is loaded with new data.

If the RFDL Receive Data register is read while there is no valid data, then a

FIFO underrun condition occurs. The underrun condition is reflected in the Status

immediately following the Received Data register read which caused the

underrun condition.

PM7344 Datasheet(PDF) 155 Page - PMC-Sierra, Inc