PM7344 datasheet(154/293 Pages) PMC

154 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

138

Registers 03AH, 13AH, 23AH and 33AH: RFDL Status

Bit

Type

Function

Default

Bit 7

Bit 6

OVR

Bit 5

FLG

Bit 4

EOM

Bit 3

CRC

Bit 2

NVB2

Bit 1

NVB1

Bit 0

NVB0

NVB[2:0]:

The NVB[2:0] bit positions indicate the number of valid bits in the RFDL

Receive Data Register byte. It is possible that not all of the bits in the

Receive Data Register are valid when the last data byte is read since the data

frame can be any number of bits in length and not necessarily an integral

number of bytes. The Receive Data Register is filled from the MSB to the

LSB bit position, with one to eight data bits being valid. The number of valid

bits is equal to 1 plus the value of NVB[2:0]. A NVB[2:0] value of 000 binary

indicates that only the MSB in the register is valid. NVB[2:0] is only valid

when the EOM bit is a logic 1 and the FLG bit is a logic 1 and the OVR bit is a

logic 0.

CRC:

The CRC bit is set if a CRC error was detected in the last received HDLC

frame. The CRC bit is only valid when EOM is logic 1 and FLG is a logic 1

and OVR is a logic 0.

On an interrupt generated from the detection of first flag, reading this register will

return invalid NVB[2:0] and CRC bits, even though the EOM bit is logic 1 and the

FLG bit is logic 1.

EOM:

The End of Message bit (EOM) follows the RDLEOM[x] output. It is set

when:

1) The last byte in the HDLC frame (EOM) is being read from the RFDL

Receive Data Register,

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