PM7350 datasheet(49/241 Pages) PMC

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PM7350 S/UNI-DUPLEX

DATA SHEET

PMC-1980581

ISSUE 5

DUAL SERIAL LINK PHY MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Ball

Name

Type

Ball

No.

Function

High Speed LVDS Links

OADDR[4]

OADDR[3]

OADDR[2]

OADDR[1]

OADDR[0]

I/O

M10

N10

L10

P11

As a SCI-PHY/Utopia bus master (OMASTER = 1,

0ANYPHY = 0) the OADDR[4:0] signals are used to

address up to 32 PHY devices for the purposes of

polling and selection for cell transfer. When

conducting polling, in order to avoid bus contention,

the S/UNI-DUPLEX inserts gap cycles during which

the OADDR[4:0] bus is set to 0x1F and OAVALID is

logic 0. When this occurs, no PHY device should

drive OCA during the following clock cycle. The

polling order is based on the existence of cells in

the downstream cell buffer. The PHY device

selected for transfer is based on the OADDR[4:0]

value present during the last cycle OENB is high.

As a bus slave the OADDR[4:0] signals are inputs.

When OAVALID is sampled high in SCI-PHY/Utopia

or low in Any-PHY configuration and the sampled

OADDR[4:0] matches the OAD[4:0] bits in the

Output Address Match register, OCA is asserted if

at least one cell is available for transfer. OCA is

delayed by an additional OFCLK cycle in Any-PHY

configuration. If the OADDR[4:0] value equals the

state of the OAD[4:0] bits in the Output Address

Match register when the OENB is last sampled

high, the S/UNI-DUPLEX will initiate a cell transfer.

As a SCI-PHY/Utopia bus slave (OMASTER = 0,

OANYPHY = 0) the device must be reselected to

resume a cell transferred that has been halted by

deasserting OENB high.

The OADDR[4:0] bus is sampled or updated on the

rising edge of OFCLK.

These signals are only active if the SCIANY input is

a logic high.

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