PM7350 datasheet(97/241 Pages) PMC

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PM7350 S/UNI-DUPLEX

DATA SHEET

PMC-1980581

ISSUE 5

DUAL SERIAL LINK PHY MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Bit

Type

Function

Default

Bit 7

R/W

RESET

Bit 6

TYPE[2]

Bit 5

TYPE[1]

Bit 4

TYPE[0]

Bit 3

ID[3]

Bit 2

ID[2]

Bit 1

ID[1]

Bit 0

ID[0]

This register allows the revision number of the S/UNI-DUPLEX to be read by

software permitting graceful migration to newer, feature-enhanced versions of

the S/UNI-DUPLEX.

In addition, writing to this register simultaneously loads all the performance meter

registers in the S/UNI-DUPLEX.

ID[3:0]:

The ID bits can be read to provide a binary S/UNI-DUPLEX revision number.

TYPE[2:0]:

The TYPE bits can be read to distinguish the S/UNI-DUPLEX from the other

members of the S/UNI family of devices.

RESET:

The RESET bit allows the S/UNI-DUPLEX to be reset under software control.

If the RESET bit is a logic one, the entire S/UNI-DUPLEX is held in reset.

This bit is not self-clearing. Therefore, a logic zero must be written to bring

the S/UNI-DUPLEX out of reset. Holding the S/UNI-DUPLEX in a reset state

places it into a low power, stand-by mode. A hardware reset clears the

RESET bit, thus negating the software reset. Otherwise, the effect of a

software reset is equivalent to that of a hardware reset.

PM7350 Datasheet(PDF) 97 Page - PMC-Sierra, Inc

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