PM7350 datasheet(89/241 Pages) PMC

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PM7350 S/UNI-DUPLEX

DATA SHEET

PMC-1980581

ISSUE 5

DUAL SERIAL LINK PHY MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

registers can be accessed through this port. Test mode registers are used to

enhance the testability of the S/UNI-DUPLEX.

The interface has a 8-bit wide data bus. Multiplexed address and data operation

is supported.

9.7.1 Inband Communication

A cell insertion and extraction capability provides a simple unacknowledged cell

relay capability. For a fully robust control channel implementation, it is assumed

the local microprocessor and the remote entity are running a reliable

communications protocol.

In the upstream direction, identical copies of each control channel cell are

broadcast on both the active and spare high-speed serial links. If the user wishes

to implement two independent control channels (active/inactive or link 1/link 2)

then the contents of the cell will have to indicate the cell’s destination link. In the

downstream direction, each high-speed serial link has a dedicated receive queue

for the control channel cells.

The control channel is treated as a virtual PHY device. In the upstream

direction, it is scheduled with the same priority as the other logical channels.

Flow control with the receiving device (either a S/UNI-VORTEX or a S/UNI-

DUPLEX) is based on the cell available bit (UPCA, see Table 16) of the high-

speed serial link marked as active. In the downstream direction, control channel

cells are queued in a four cell FIFO for each high-speed serial link. If either FIFO

contains two or more cells, the cell available bit returned upstream on the

corresponding high-speed link is deasserted to prevent cell loss when the

microprocessor cell reads fail to keep pace with the incoming control channel

cells.

9.7.2 Writing Cells

The S/UNI-DUPLEX contains a two cell buffer for the insertion of a cell by the

microprocessor into the high-speed serial interface. Optional CRC-32 calculation

over the last 48 bytes of the cell relieves the microprocessor of this task. The

CRC-32 generator polynomial is consistent with AAL5:

5. G(x) = x

32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x

+ 1

All cells written by the microprocessor will have binary 111110 encoded in the

PHYID[5:0] field within the cell prepend bytes. This distinction between user

cells and control cells provides a clear channel for both types of cells.

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