PM7350 datasheet(60/241 Pages) PMC

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RELEASED

PM7350 S/UNI-DUPLEX

DATA SHEET

PMC-1980581

ISSUE 5

DUAL SERIAL LINK PHY MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Table 2 Eight Bit SCI-PHY/Utopia Bus Master, Input Configuration

Byte

bytes

7 H5UDF PRELEN

Notes

Short cell, no H5 byte

Default, Utopia compatible

1 user byte then H1-H4

1 user byte then H1-H5

2 user bytes then H1-H4.

2 user bytes then H1-H5.

Table 3 Sixteen Bit SCI-PHY/Utopia Bus Master, Input Configuration

Word

bytes

H5UDF

PRELEN

Notes

Short cell, no H5/UDF field

Default, Utopia compatible

1 user word then H1-H4

1 user word, H1-H4, then H5/UDF

In the egress direction (cells are transferred from the LVDS link to the output

bus.), only those PHY devices are polled for which there is a cell in the internal

cell buffer. The cell buffer is organized as 32 FIFOs, each associated with a

single PHY device. This arrangement prevents head-of-line blocking. As per the

ingress interface, transfers are cell based and polling is concurrent with cell

transfers.

The SCI-PHY/Any-PHY Output Configuration register (0x14) determines the cell

format of the output bus. A SCI-PHY/Utopia bus master neither requires nor

supports embedded PHY ID. The cell length options for the 8 bit bus (shown in

Fig. 6) are described in Table 4. 16 bit bus options (shown in Fig. 7) are

described in Table 5.

PM7350 Datasheet(PDF) 60 Page - PMC-Sierra, Inc