PM7350 datasheet(79/241 Pages) PMC

79 / 241 page

RELEASED

PM7350 S/UNI-DUPLEX

DATA SHEET

PMC-1980581

ISSUE 5

DUAL SERIAL LINK PHY MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

after clock recovery. Setting the DLB bit corresponding to the inactive link has no

effect.

The metallic loopback is set independently on each high-speed serial link. It can

be effected in one of three ways: after the receipt of the loopback activate code

on the corresponding RXD1+/- or RXD2+/- inputs (as described in Section 9.3.2)

when the corresponding MLB1 or MLB2 bit of the Serial Link Maintenance

loopback occurs at the LVDS transceiver after the conversion to digital but before

clock recovery. The looped back data may be slightly distorted by the data

slicing (differential to single-ended) and re-buffering that occurs.

Metallic loopback is terminated if a loopback deactivate bit oriented code is

received and validated, provided the corresponding MLB1 or MLB2 bit of the

Serial Links Maintenance register to logic 0.

9.3.1 Link Integrity Monitoring

Although the serial link bit error rate can be inferred from the accumulated

Header Check Sequence (HCS) errors, the option exists to perform error

monitoring over the entire bit stream.

When the feature is enabled the second User Prepend byte transmitted shall be

overwritten by the CRC-8 syndrome for the preceding cell. The encoding is valid

for all cells, including stuff cells. The CRC-8 polynomial is x8 + x2 + x + 1. The

receiver shall raise a maskable interrupt and optionally increment the HCS error

count. Simultaneous HCS and cell CRC-8 errors result in a single increment.

9.3.2 Bit Oriented Codes

Bit Oriented Codes (BOCs) are carried in the BOC bit position in the System

Prepend. The 63 possible codes can be used to carry predefined or user

defined signaling.

Bit oriented codes are transmitted as a repeating 16-bit sequence consisting of 8

ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0). The code to be

transmitted is set independently on the two LVDS links, and is programmed by

writing the TXD1 Bit Oriented Code and TXD2 Bit Oriented Code registers. The

autonomously generated Remote Defect Indication (RDI) code, which is

generated upon a loss-of-signal or loss-of-cell-delineation, takes precedence

over the programmed code. RDI insertion can be disabled via the RDIDIS bit of

the Serial Links Maintenance register. RDI can be inserted manually on a high-

speed serial link by setting the corresponding TXD1 Bit Oriented Code or TXD2

Bit Oriented Code register to all zeros.

PM7350 Datasheet(PDF) 79 Page - PMC-Sierra, Inc

PM7350 Datasheet(HTML) 79 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL