TDA4VM21 datasheet(130/331 Pages) TI

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5.3.32.2.2 WKUP Domain

Table 5-120. Clock0 Signal Descriptions

SIGNAL NAME [1]

DESCRIPTION [2]

PIN TYPE

[3]

BALL [4]

WKUP_LFOSC0_XI

Low frequency (32.768 KHz) oscillator input

N28

WKUP_LFOSC0_XO

Low frequency (32.768 KHz) oscillator output

N26

WKUP_OSC0_XI

High frequency oscillator input

M29

WKUP_OSC0_XO

High frequency oscillator output

M27

5.3.32.3 System

5.3.32.3.1 MAIN Domain

Table 5-121. System0 Signal Descriptions

SIGNAL NAME [1]

DESCRIPTION [2]

PIN TYPE

[3]

BALL [4]

AUDIO_EXT_REFCLK0

External clock routed to ATL or MCASP as one of the

selectable input clock sources, or as a output clock

output for ATL or MCASP

AD22

AUDIO_EXT_REFCLK1

External clock routed to ATL or MCASP as one of the

selectable input clock sources, or as a output clock

output for ATL or MCASP

AE20

AUDIO_EXT_REFCLK2

External clock routed to ATL or MCASP as one of the

selectable input clock sources, or as a output clock

output for ATL or MCASP

W26

AUDIO_EXT_REFCLK3

External clock routed to ATL or MCASP as one of the

selectable input clock sources, or as a output clock

output for ATL or MCASP

W25

EXTINTn

External Interrupt

AC18

EXT_REFCLK1

External clock input to MAIN domain, routed to Timer

clock muxes as one of the selectable input clock

sources for Timer/WDT modules, or as reference clock

to MAIN_PLL2 (PER1 PLL)

OBSCLK0

Observation clock output for test and debug purposes

only

OBSCLK1

Observation clock output for test and debug purposes

only

AB24

OBSCLK2

Observation clock output for test and debug purposes

only

AD21

PORz_OUT

MAIN domain POR status output

RESETSTATz

MAIN domain warm reset status output

SOC_SAFETY_ERRORn

Error signal output from MAIN domain ESM

SYSCLKOUT0

SYSCLK0 output from MAIN PLL controller (divided by 6)

for test and debug purposes only

VMON_ER_VSYS

Voltage Monitor for System supply, requires External

Resistor divider

M26

VMON_IR_VEXT

Voltage Monitor for External 1.8V supply, uses Internal

Resistor divider

V19

5.3.32.3.2 WKUP Domain

Table 5-122. System0 Signal Descriptions

SIGNAL NAME [1]

DESCRIPTION [2]

PIN TYPE

[3]

BALL [4]

MCU_CLKOUT0

Reference clock output for Ethernet PHYs (50MHz or

25MHz)

H27

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

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